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git01.mediatek.com / filogic / uboot / d02ea501953103cf4ca969b923d01aa73d4ceb7d / . / dts / upstream / src / arm64 / freescale / imx8mm-verdin.dtsi
blob: 5fa39591419115f7e0a4a1cf81df0248c58382fb [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include <dt-bindings/phy/phy-imx8-pcie.h>
7#include <dt-bindings/pwm/pwm.h>
8#include "imx8mm.dtsi"
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]9#include "imx8mm-overdrive.dtsi"
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]10
11/ {
12 chosen {
13 stdout-path = &uart1;
14 };
15
16 aliases {
17 rtc0 = &rtc_i2c;
18 rtc1 = &snvs_rtc;
19 };
20
21 backlight: backlight {
22 compatible = "pwm-backlight";
23 brightness-levels = <0 45 63 88 119 158 203 255>;
24 default-brightness-level = <4>;
25 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
26 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
29 power-supply = <&reg_3p3v>;
30 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
31 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
32 status = "disabled";
33 };
34
35 /* Fixed clock dedicated to SPI CAN controller */
36 clk40m: oscillator {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <40000000>;
40 };
41
42 gpio-keys {
43 compatible = "gpio-keys";
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_gpio_keys>;
46
47 key-wakeup {
48 debounce-interval = <10>;
49 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
50 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
51 label = "Wake-Up";
52 linux,code = <KEY_WAKEUP>;
53 wakeup-source;
54 };
55 };
56
57 hdmi_connector: hdmi-connector {
58 compatible = "hdmi-connector";
59 ddc-i2c-bus = <&i2c2>;
60 /* Verdin PWM_3_DSI (SODIMM 19) */
61 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
62 label = "hdmi";
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
65 type = "a";
66 status = "disabled";
67 };
68
69 panel_lvds: panel-lvds {
70 compatible = "panel-lvds";
71 backlight = <&backlight>;
72 data-mapping = "vesa-24";
73 status = "disabled";
74 };
75
76 /* Carrier Board Supplies */
77 reg_1p8v: regulator-1p8v {
78 compatible = "regulator-fixed";
79 regulator-max-microvolt = <1800000>;
80 regulator-min-microvolt = <1800000>;
81 regulator-name = "+V1.8_SW";
82 };
83
84 reg_3p3v: regulator-3p3v {
85 compatible = "regulator-fixed";
86 regulator-max-microvolt = <3300000>;
87 regulator-min-microvolt = <3300000>;
88 regulator-name = "+V3.3_SW";
89 };
90
91 reg_5p0v: regulator-5p0v {
92 compatible = "regulator-fixed";
93 regulator-max-microvolt = <5000000>;
94 regulator-min-microvolt = <5000000>;
95 regulator-name = "+V5_SW";
96 };
97
98 /* Non PMIC On-module Supplies */
99 reg_ethphy: regulator-ethphy {
100 compatible = "regulator-fixed";
101 enable-active-high;
102 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
103 off-on-delay-us = <500000>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_reg_eth>;
106 regulator-always-on;
107 regulator-boot-on;
108 regulator-max-microvolt = <3300000>;
109 regulator-min-microvolt = <3300000>;
110 regulator-name = "On-module +V3.3_ETH";
111 startup-delay-us = <200000>;
112 };
113
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]114 /*
115 * By default we enable CTRL_SLEEP_MOCI#, this is required to have
116 * peripherals on the carrier board powered.
117 * If more granularity or power saving is required this can be disabled
118 * in the carrier board device tree files.
119 */
120 reg_force_sleep_moci: regulator-force-sleep-moci {
121 compatible = "regulator-fixed";
122 enable-active-high;
123 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
124 gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
125 regulator-always-on;
126 regulator-boot-on;
127 regulator-name = "CTRL_SLEEP_MOCI#";
128 };
129
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]130 reg_usb_otg1_vbus: regulator-usb-otg1 {
131 compatible = "regulator-fixed";
132 enable-active-high;
133 /* Verdin USB_1_EN (SODIMM 155) */
134 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_reg_usb1_en>;
137 regulator-max-microvolt = <5000000>;
138 regulator-min-microvolt = <5000000>;
139 regulator-name = "USB_1_EN";
140 };
141
142 reg_usb_otg2_vbus: regulator-usb-otg2 {
143 compatible = "regulator-fixed";
144 enable-active-high;
145 /* Verdin USB_2_EN (SODIMM 185) */
146 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_reg_usb2_en>;
149 regulator-max-microvolt = <5000000>;
150 regulator-min-microvolt = <5000000>;
151 regulator-name = "USB_2_EN";
152 };
153
154 reg_usdhc2_vmmc: regulator-usdhc2 {
155 compatible = "regulator-fixed";
156 enable-active-high;
157 /* Verdin SD_1_PWR_EN (SODIMM 76) */
158 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
159 off-on-delay-us = <100000>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
162 regulator-max-microvolt = <3300000>;
163 regulator-min-microvolt = <3300000>;
164 regulator-name = "+V3.3_SD";
165 startup-delay-us = <2000>;
166 };
167
168 reserved-memory {
169 #address-cells = <2>;
170 #size-cells = <2>;
171 ranges;
172
173 /* Use the kernel configuration settings instead */
174 /delete-node/ linux,cma;
175 };
176};
177
178&A53_0 {
179 cpu-supply = <&reg_vdd_arm>;
180};
181
182&A53_1 {
183 cpu-supply = <&reg_vdd_arm>;
184};
185
186&A53_2 {
187 cpu-supply = <&reg_vdd_arm>;
188};
189
190&A53_3 {
191 cpu-supply = <&reg_vdd_arm>;
192};
193
194&cpu_alert0 {
195 temperature = <95000>;
196};
197
198&cpu_crit0 {
199 temperature = <105000>;
200};
201
202&ddrc {
203 operating-points-v2 = <&ddrc_opp_table>;
204
205 ddrc_opp_table: opp-table {
206 compatible = "operating-points-v2";
207
208 opp-25000000 {
209 opp-hz = /bits/ 64 <25000000>;
210 };
211
212 opp-100000000 {
213 opp-hz = /bits/ 64 <100000000>;
214 };
215
216 opp-750000000 {
217 opp-hz = /bits/ 64 <750000000>;
218 };
219 };
220};
221
222/* Verdin SPI_1 */
223&ecspi2 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_ecspi2>;
229};
230
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]231/* On-module SPI */
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]232&ecspi3 {
233 #address-cells = <1>;
234 #size-cells = <0>;
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]235 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]236 pinctrl-names = "default";
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]237 pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_tpm_spi_cs>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]238 status = "okay";
239
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]240 /* Verdin CAN_1 */
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]241 can1: can@0 {
242 compatible = "microchip,mcp251xfd";
243 clocks = <&clk40m>;
244 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_can1_int>;
247 reg = <0>;
248 spi-max-frequency = <8500000>;
249 };
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]250
251 verdin_som_tpm: tpm@1 {
252 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
253 reg = <0x1>;
254 spi-max-frequency = <36000000>;
255 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]256};
257
258/* Verdin ETH_1 (On-module PHY) */
259&fec1 {
260 fsl,magic-packet;
261 phy-handle = <&ethphy0>;
262 phy-mode = "rgmii-id";
263 phy-supply = <&reg_ethphy>;
264 pinctrl-names = "default", "sleep";
265 pinctrl-0 = <&pinctrl_fec1>;
266 pinctrl-1 = <&pinctrl_fec1_sleep>;
267
268 mdio {
269 #address-cells = <1>;
270 #size-cells = <0>;
271
272 ethphy0: ethernet-phy@7 {
273 compatible = "ethernet-phy-ieee802.3-c22";
274 interrupt-parent = <&gpio1>;
275 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
276 micrel,led-mode = <0>;
277 reg = <7>;
278 };
279 };
280};
281
282/* Verdin QSPI_1 */
283&flexspi {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_flexspi0>;
286};
287
288&gpio1 {
289 gpio-line-names = "SODIMM_216",
290 "SODIMM_19",
291 "",
292 "",
293 "",
294 "",
295 "",
296 "",
297 "SODIMM_220",
298 "SODIMM_222",
299 "",
300 "SODIMM_218",
301 "SODIMM_155",
302 "SODIMM_157",
303 "SODIMM_185",
304 "SODIMM_187";
305};
306
307&gpio2 {
308 gpio-line-names = "",
309 "",
310 "",
311 "",
312 "",
313 "",
314 "",
315 "",
316 "",
317 "",
318 "",
319 "",
320 "SODIMM_84",
321 "SODIMM_78",
322 "SODIMM_74",
323 "SODIMM_80",
324 "SODIMM_82",
325 "SODIMM_70",
326 "SODIMM_72";
327};
328
329&gpio5 {
330 gpio-line-names = "SODIMM_131",
331 "",
332 "SODIMM_91",
333 "SODIMM_16",
334 "SODIMM_15",
335 "SODIMM_208",
336 "SODIMM_137",
337 "SODIMM_139",
338 "SODIMM_141",
339 "SODIMM_143",
340 "SODIMM_196",
341 "SODIMM_200",
342 "SODIMM_198",
343 "SODIMM_202",
344 "",
345 "",
346 "SODIMM_55",
347 "SODIMM_53",
348 "SODIMM_95",
349 "SODIMM_93",
350 "SODIMM_14",
351 "SODIMM_12",
352 "",
353 "",
354 "",
355 "",
356 "SODIMM_210",
357 "SODIMM_212",
358 "SODIMM_151",
359 "SODIMM_153";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]360};
361
362/* On-module I2C */
363&i2c1 {
364 clock-frequency = <400000>;
365 pinctrl-names = "default", "gpio";
366 pinctrl-0 = <&pinctrl_i2c1>;
367 pinctrl-1 = <&pinctrl_i2c1_gpio>;
368 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
369 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
370 status = "okay";
371
372 pca9450: pmic@25 {
373 compatible = "nxp,pca9450a";
374 interrupt-parent = <&gpio1>;
375 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
376 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_pmic>;
379 reg = <0x25>;
380
381 /*
382 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
383 * behind this PMIC.
384 */
385
386 regulators {
387 reg_vdd_soc: BUCK1 {
388 nxp,dvs-run-voltage = <850000>;
389 nxp,dvs-standby-voltage = <800000>;
390 regulator-always-on;
391 regulator-boot-on;
392 regulator-max-microvolt = <850000>;
393 regulator-min-microvolt = <800000>;
394 regulator-name = "On-module +VDD_SOC (BUCK1)";
395 regulator-ramp-delay = <3125>;
396 };
397
398 reg_vdd_arm: BUCK2 {
399 nxp,dvs-run-voltage = <950000>;
400 nxp,dvs-standby-voltage = <850000>;
401 regulator-always-on;
402 regulator-boot-on;
403 regulator-max-microvolt = <1050000>;
404 regulator-min-microvolt = <805000>;
405 regulator-name = "On-module +VDD_ARM (BUCK2)";
406 regulator-ramp-delay = <3125>;
407 };
408
409 reg_vdd_dram: BUCK3 {
410 regulator-always-on;
411 regulator-boot-on;
412 regulator-max-microvolt = <1000000>;
413 regulator-min-microvolt = <805000>;
414 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
415 };
416
417 reg_vdd_3v3: BUCK4 {
418 regulator-always-on;
419 regulator-boot-on;
420 regulator-max-microvolt = <3300000>;
421 regulator-min-microvolt = <3300000>;
422 regulator-name = "On-module +V3.3 (BUCK4)";
423 };
424
425 reg_vdd_1v8: BUCK5 {
426 regulator-always-on;
427 regulator-boot-on;
428 regulator-max-microvolt = <1800000>;
429 regulator-min-microvolt = <1800000>;
430 regulator-name = "PWR_1V8_MOCI (BUCK5)";
431 };
432
433 reg_nvcc_dram: BUCK6 {
434 regulator-always-on;
435 regulator-boot-on;
436 regulator-max-microvolt = <1100000>;
437 regulator-min-microvolt = <1100000>;
438 regulator-name = "On-module +VDD_DDR (BUCK6)";
439 };
440
441 reg_nvcc_snvs: LDO1 {
442 regulator-always-on;
443 regulator-boot-on;
444 regulator-max-microvolt = <1800000>;
445 regulator-min-microvolt = <1800000>;
446 regulator-name = "On-module +V1.8_SNVS (LDO1)";
447 };
448
449 reg_vdd_snvs: LDO2 {
450 regulator-always-on;
451 regulator-boot-on;
452 regulator-max-microvolt = <800000>;
453 regulator-min-microvolt = <800000>;
454 regulator-name = "On-module +V0.8_SNVS (LDO2)";
455 };
456
457 reg_vdda: LDO3 {
458 regulator-always-on;
459 regulator-boot-on;
460 regulator-max-microvolt = <1800000>;
461 regulator-min-microvolt = <1800000>;
462 regulator-name = "On-module +V1.8A (LDO3)";
463 };
464
465 reg_vdd_phy: LDO4 {
466 regulator-always-on;
467 regulator-boot-on;
468 regulator-max-microvolt = <900000>;
469 regulator-min-microvolt = <900000>;
470 regulator-name = "On-module +V0.9_MIPI (LDO4)";
471 };
472
473 reg_nvcc_sd: LDO5 {
474 regulator-max-microvolt = <3300000>;
475 regulator-min-microvolt = <1800000>;
476 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
477 };
478 };
479 };
480
481 rtc_i2c: rtc@32 {
482 compatible = "epson,rx8130";
483 reg = <0x32>;
484 };
485
486 adc@49 {
487 compatible = "ti,ads1015";
488 reg = <0x49>;
489 #address-cells = <1>;
490 #size-cells = <0>;
491
492 /* Verdin I2C_1 (ADC_4 - ADC_3) */
493 channel@0 {
494 reg = <0>;
495 ti,datarate = <4>;
496 ti,gain = <2>;
497 };
498
499 /* Verdin I2C_1 (ADC_4 - ADC_1) */
500 channel@1 {
501 reg = <1>;
502 ti,datarate = <4>;
503 ti,gain = <2>;
504 };
505
506 /* Verdin I2C_1 (ADC_3 - ADC_1) */
507 channel@2 {
508 reg = <2>;
509 ti,datarate = <4>;
510 ti,gain = <2>;
511 };
512
513 /* Verdin I2C_1 (ADC_2 - ADC_1) */
514 channel@3 {
515 reg = <3>;
516 ti,datarate = <4>;
517 ti,gain = <2>;
518 };
519
520 /* Verdin I2C_1 ADC_4 */
521 channel@4 {
522 reg = <4>;
523 ti,datarate = <4>;
524 ti,gain = <2>;
525 };
526
527 /* Verdin I2C_1 ADC_3 */
528 channel@5 {
529 reg = <5>;
530 ti,datarate = <4>;
531 ti,gain = <2>;
532 };
533
534 /* Verdin I2C_1 ADC_2 */
535 channel@6 {
536 reg = <6>;
537 ti,datarate = <4>;
538 ti,gain = <2>;
539 };
540
541 /* Verdin I2C_1 ADC_1 */
542 channel@7 {
543 reg = <7>;
544 ti,datarate = <4>;
545 ti,gain = <2>;
546 };
547 };
548
549 eeprom@50 {
550 compatible = "st,24c02";
551 pagesize = <16>;
552 reg = <0x50>;
553 };
554};
555
556/* Verdin I2C_2_DSI */
557&i2c2 {
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]558 clock-frequency = <400000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]559 pinctrl-names = "default", "gpio";
560 pinctrl-0 = <&pinctrl_i2c2>;
561 pinctrl-1 = <&pinctrl_i2c2_gpio>;
562 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
563 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
564 status = "disabled";
565};
566
567/* Verdin I2C_3_HDMI N/A */
568
569/* Verdin I2C_4_CSI */
570&i2c3 {
571 clock-frequency = <400000>;
572 pinctrl-names = "default", "gpio";
573 pinctrl-0 = <&pinctrl_i2c3>;
574 pinctrl-1 = <&pinctrl_i2c3_gpio>;
575 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
576 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
577};
578
579/* Verdin I2C_1 */
580&i2c4 {
581 clock-frequency = <400000>;
582 pinctrl-names = "default", "gpio";
583 pinctrl-0 = <&pinctrl_i2c4>;
584 pinctrl-1 = <&pinctrl_i2c4_gpio>;
585 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
586 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
587
588 gpio_expander_21: gpio-expander@21 {
589 compatible = "nxp,pcal6416";
590 #gpio-cells = <2>;
591 gpio-controller;
592 reg = <0x21>;
593 vcc-supply = <&reg_3p3v>;
594 status = "disabled";
595 };
596
597 lvds_ti_sn65dsi84: bridge@2c {
598 compatible = "ti,sn65dsi84";
599 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
600 /* Verdin GPIO_10_DSI (SODIMM 21) */
601 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
604 reg = <0x2c>;
605 status = "disabled";
606 };
607
608 /* Current measurement into module VCC */
609 hwmon: hwmon@40 {
610 compatible = "ti,ina219";
611 reg = <0x40>;
612 shunt-resistor = <10000>;
613 status = "disabled";
614 };
615
616 hdmi_lontium_lt8912: hdmi@48 {
617 compatible = "lontium,lt8912b";
618 pinctrl-names = "default";
619 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
620 reg = <0x48>;
621 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
622 /* Verdin GPIO_10_DSI (SODIMM 21) */
623 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
624 status = "disabled";
625 };
626
627 atmel_mxt_ts: touch@4a {
628 compatible = "atmel,maxtouch";
629 /*
630 * Verdin GPIO_9_DSI
631 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
632 */
633 interrupt-parent = <&gpio3>;
634 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
637 reg = <0x4a>;
638 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
639 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
640 status = "disabled";
641 };
642
643 /* Temperature sensor on carrier board */
644 hwmon_temp: sensor@4f {
645 compatible = "ti,tmp75c";
646 reg = <0x4f>;
647 status = "disabled";
648 };
649
650 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
651 eeprom_display_adapter: eeprom@50 {
652 compatible = "st,24c02";
653 pagesize = <16>;
654 reg = <0x50>;
655 status = "disabled";
656 };
657
658 /* EEPROM on carrier board */
659 eeprom_carrier_board: eeprom@57 {
660 compatible = "st,24c02";
661 pagesize = <16>;
662 reg = <0x57>;
663 status = "disabled";
664 };
665};
666
667/* Verdin PCIE_1 */
668&pcie0 {
669 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
670 <&clk IMX8MM_CLK_PCIE1_CTRL>;
671 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
672 <&clk IMX8MM_SYS_PLL2_250M>;
673 assigned-clock-rates = <10000000>, <250000000>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&pinctrl_pcie0>;
676 /* PCIE_1_RESET# (SODIMM 244) */
677 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
678};
679
680&pcie_phy {
681 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
682 clock-names = "ref";
683 fsl,clkreq-unsupported;
684 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
685 fsl,tx-deemph-gen1 = <0x2d>;
686 fsl,tx-deemph-gen2 = <0xf>;
687};
688
689/* Verdin PWM_3_DSI */
690&pwm1 {
691 pinctrl-names = "default";
692 pinctrl-0 = <&pinctrl_pwm_1>;
693 #pwm-cells = <3>;
694};
695
696/* Verdin PWM_1 */
697&pwm2 {
698 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_pwm_2>;
700 #pwm-cells = <3>;
701};
702
703/* Verdin PWM_2 */
704&pwm3 {
705 pinctrl-names = "default";
706 pinctrl-0 = <&pinctrl_pwm_3>;
707 #pwm-cells = <3>;
708};
709
710/* Verdin I2S_1 */
711&sai2 {
712 #sound-dai-cells = <0>;
713 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
714 assigned-clock-rates = <24576000>;
715 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
716 pinctrl-names = "default";
717 pinctrl-0 = <&pinctrl_sai2>;
718};
719
720&snvs_pwrkey {
721 status = "okay";
722};
723
724/* Verdin UART_3, used as the Linux console */
725&uart1 {
726 pinctrl-names = "default";
727 pinctrl-0 = <&pinctrl_uart1>;
728};
729
730/* Verdin UART_1 */
731&uart2 {
732 pinctrl-names = "default";
733 pinctrl-0 = <&pinctrl_uart2>;
734 uart-has-rtscts;
735};
736
737/* Verdin UART_2 */
738&uart3 {
739 pinctrl-names = "default";
740 pinctrl-0 = <&pinctrl_uart3>;
741 uart-has-rtscts;
742};
743
744/*
745 * Verdin UART_4
746 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
747 */
748&uart4 {
749 pinctrl-names = "default";
750 pinctrl-0 = <&pinctrl_uart4>;
751};
752
753/* Verdin USB_1 */
754&usbotg1 {
755 adp-disable;
756 dr_mode = "otg";
757 hnp-disable;
758 samsung,picophy-dc-vol-level-adjust = <7>;
759 samsung,picophy-pre-emp-curr-control = <3>;
760 srp-disable;
761 vbus-supply = <&reg_usb_otg1_vbus>;
762};
763
764/* Verdin USB_2 */
765&usbotg2 {
766 dr_mode = "host";
767 samsung,picophy-dc-vol-level-adjust = <7>;
768 samsung,picophy-pre-emp-curr-control = <3>;
769 vbus-supply = <&reg_usb_otg2_vbus>;
770};
771
772&usbphynop1 {
773 vcc-supply = <&reg_vdd_3v3>;
774};
775
776&usbphynop2 {
777 power-domains = <&pgc_otg2>;
778 vcc-supply = <&reg_vdd_3v3>;
779};
780
781/* On-module eMMC */
782&usdhc1 {
783 bus-width = <8>;
784 keep-power-in-suspend;
785 non-removable;
786 pinctrl-names = "default", "state_100mhz", "state_200mhz";
787 pinctrl-0 = <&pinctrl_usdhc1>;
788 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
789 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
790 status = "okay";
791};
792
793/* Verdin SD_1 */
794&usdhc2 {
795 bus-width = <4>;
796 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
797 disable-wp;
798 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
799 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
800 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
801 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
802 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
803 vmmc-supply = <&reg_usdhc2_vmmc>;
804};
805
806&wdog1 {
807 fsl,ext-reset-output;
808 pinctrl-names = "default";
809 pinctrl-0 = <&pinctrl_wdog>;
810 status = "okay";
811};
812
813&iomuxc {
814 pinctrl-names = "default";
815 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
816 <&pinctrl_gpio3>, <&pinctrl_gpio4>,
817 <&pinctrl_gpio7>, <&pinctrl_gpio8>,
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]818 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]819
820 pinctrl_can1_int: can1intgrp {
821 fsl,pins =
822 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */
823 };
824
825 pinctrl_can2_int: can2intgrp {
826 fsl,pins =
827 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
828 };
829
830 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
831 fsl,pins =
832 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */
833 };
834
835 pinctrl_ecspi2: ecspi2grp {
836 fsl,pins =
837 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
838 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
839 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
840 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
841 };
842
843 pinctrl_ecspi3: ecspi3grp {
844 fsl,pins =
845 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
846 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
847 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
848 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
849 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
850 };
851
852 pinctrl_fec1: fec1grp {
853 fsl,pins =
854 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
855 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
856 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
857 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
858 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
859 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
860 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
861 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
862 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
863 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
864 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
865 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
866 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
867 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
868 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
869 };
870
871 pinctrl_fec1_sleep: fec1-sleepgrp {
872 fsl,pins =
873 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
874 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
875 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
876 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
877 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
878 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
879 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
880 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
881 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
882 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
883 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
884 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
885 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
886 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
887 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
888 };
889
890 pinctrl_flexspi0: flexspi0grp {
891 fsl,pins =
892 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
893 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
894 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
895 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
896 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
897 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
898 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
899 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
900 };
901
902 pinctrl_gpio1: gpio1grp {
903 fsl,pins =
904 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
905 };
906
907 pinctrl_gpio2: gpio2grp {
908 fsl,pins =
909 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */
910 };
911
912 pinctrl_gpio3: gpio3grp {
913 fsl,pins =
914 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */
915 };
916
917 pinctrl_gpio4: gpio4grp {
918 fsl,pins =
919 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */
920 };
921
922 pinctrl_gpio5: gpio5grp {
923 fsl,pins =
924 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */
925 };
926
927 pinctrl_gpio6: gpio6grp {
928 fsl,pins =
929 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */
930 };
931
932 pinctrl_gpio7: gpio7grp {
933 fsl,pins =
934 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */
935 };
936
937 pinctrl_gpio8: gpio8grp {
938 fsl,pins =
939 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */
940 };
941
942 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
943 pinctrl_gpio_9_dsi: gpio9dsigrp {
944 fsl,pins =
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]945 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c6>; /* SODIMM 17 */
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]946 };
947
948 /* Verdin GPIO_10_DSI (pulled-up as active-low) */
949 pinctrl_gpio_10_dsi: gpio10dsigrp {
950 fsl,pins =
951 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */
952 };
953
954 pinctrl_gpio_hog1: gpiohog1grp {
955 fsl,pins =
956 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */
957 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */
958 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */
959 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */
960 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */
961 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */
962 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */
963 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */
964 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */
965 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */
966 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */
967 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */
968 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */
969 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */
970 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */
971 };
972
973 pinctrl_gpio_hog2: gpiohog2grp {
974 fsl,pins =
975 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */
976 };
977
978 pinctrl_gpio_hog3: gpiohog3grp {
979 fsl,pins =
980 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */
981 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */
982 };
983
984 pinctrl_gpio_keys: gpiokeysgrp {
985 fsl,pins =
986 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */
987 };
988
989 /* On-module I2C */
990 pinctrl_i2c1: i2c1grp {
991 fsl,pins =
992 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */
993 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */
994 };
995
996 pinctrl_i2c1_gpio: i2c1gpiogrp {
997 fsl,pins =
998 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */
999 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */
1000 };
1001
1002 /* Verdin I2C_4_CSI */
1003 pinctrl_i2c2: i2c2grp {
1004 fsl,pins =
1005 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */
1006 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */
1007 };
1008
1009 pinctrl_i2c2_gpio: i2c2gpiogrp {
1010 fsl,pins =
1011 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */
1012 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */
1013 };
1014
1015 /* Verdin I2C_2_DSI */
1016 pinctrl_i2c3: i2c3grp {
1017 fsl,pins =
1018 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */
1019 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */
1020 };
1021
1022 pinctrl_i2c3_gpio: i2c3gpiogrp {
1023 fsl,pins =
1024 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */
1025 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */
1026 };
1027
1028 /* Verdin I2C_1 */
1029 pinctrl_i2c4: i2c4grp {
1030 fsl,pins =
1031 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */
1032 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */
1033 };
1034
1035 pinctrl_i2c4_gpio: i2c4gpiogrp {
1036 fsl,pins =
1037 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */
1038 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */
1039 };
1040
1041 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1042 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1043 fsl,pins =
1044 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */
1045 };
1046
1047 /* Verdin I2S_2_D_OUT shared with SAI5 */
1048 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1049 fsl,pins =
1050 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */
1051 };
1052
1053 pinctrl_pcie0: pcie0grp {
1054 fsl,pins =
1055 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */
1056 /* PMIC_EN_PCIe_CLK, unused */
1057 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>;
1058 };
1059
1060 pinctrl_pmic: pmicirqgrp {
1061 fsl,pins =
1062 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */
1063 };
1064
1065 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */
1066 pinctrl_pwm_1: pwm1grp {
1067 fsl,pins =
1068 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */
1069 };
1070
1071 pinctrl_pwm_2: pwm2grp {
1072 fsl,pins =
1073 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */
1074 };
1075
1076 pinctrl_pwm_3: pwm3grp {
1077 fsl,pins =
1078 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */
1079 };
1080
1081 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
1082 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
1083 fsl,pins =
1084 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */
1085 };
1086
1087 pinctrl_reg_eth: regethgrp {
1088 fsl,pins =
1089 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */
1090 };
1091
1092 pinctrl_reg_usb1_en: regusb1engrp {
1093 fsl,pins =
1094 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */
1095 };
1096
1097 pinctrl_reg_usb2_en: regusb2engrp {
1098 fsl,pins =
1099 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */
1100 };
1101
1102 pinctrl_sai2: sai2grp {
1103 fsl,pins =
1104 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
1105 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
1106 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
1107 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
1108 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
1109 };
1110
1111 pinctrl_sai5: sai5grp {
1112 fsl,pins =
1113 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */
1114 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */
1115 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */
1116 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */
1117 };
1118
1119 /* control signal for optional ATTPM20P or SE050 */
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]1120 pinctrl_tpm_spi_cs: tpmspicsgrp {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1121 fsl,pins =
1122 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
1123 };
1124
1125 pinctrl_tsp: tspgrp {
1126 fsl,pins =
1127 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */
1128 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */
1129 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */
1130 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */
1131 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */
1132 };
1133
1134 pinctrl_uart1: uart1grp {
1135 fsl,pins =
1136 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
1137 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
1138 };
1139
1140 pinctrl_uart2: uart2grp {
1141 fsl,pins =
1142 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
1143 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
1144 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
1145 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
1146 };
1147
1148 pinctrl_uart3: uart3grp {
1149 fsl,pins =
1150 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
1151 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
1152 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
1153 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
1154 };
1155
1156 pinctrl_uart4: uart4grp {
1157 fsl,pins =
1158 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */
1159 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */
1160 };
1161
1162 pinctrl_usdhc1: usdhc1grp {
1163 fsl,pins =
1164 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>,
1165 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>,
1166 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>,
1167 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>,
1168 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>,
1169 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>,
1170 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>,
1171 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>,
1172 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>,
1173 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>,
1174 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1175 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>;
1176 };
1177
1178 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1179 fsl,pins =
1180 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>,
1181 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>,
1182 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>,
1183 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>,
1184 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>,
1185 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>,
1186 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>,
1187 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>,
1188 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>,
1189 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>,
1190 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1191 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>;
1192 };
1193
1194 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1195 fsl,pins =
1196 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>,
1197 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>,
1198 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>,
1199 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>,
1200 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>,
1201 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>,
1202 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>,
1203 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>,
1204 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>,
1205 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>,
1206 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
1207 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>;
1208 };
1209
1210 pinctrl_usdhc2_cd: usdhc2cdgrp {
1211 fsl,pins =
1212 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
1213 };
1214
1215 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1216 fsl,pins =
1217 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */
1218 };
1219
1220 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1221 fsl,pins =
1222 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
1223 };
1224
1225 /*
1226 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
1227 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
1228 */
1229 pinctrl_usdhc2: usdhc2grp {
1230 fsl,pins =
1231 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1232 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
1233 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
1234 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
1235 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
1236 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
1237 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
1238 };
1239
1240 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1241 fsl,pins =
1242 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1243 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
1244 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
1245 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
1246 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
1247 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
1248 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
1249 };
1250
1251 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1252 fsl,pins =
1253 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
1254 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
1255 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
1256 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
1257 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
1258 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
1259 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
1260 };
1261
1262 /* Avoid backfeeding with removed card power */
1263 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1264 fsl,pins =
1265 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
1266 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
1267 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
1268 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
1269 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>,
1270 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>,
1271 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>;
1272 };
1273
1274 /*
1275 * On-module Wi-Fi/BT or type specific SDHC interface
1276 * (e.g. on X52 extension slot of Verdin Development Board)
1277 */
1278 pinctrl_usdhc3: usdhc3grp {
1279 fsl,pins =
1280 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
1281 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
1282 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
1283 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
1284 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
1285 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
1286 };
1287
1288 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1289 fsl,pins =
1290 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
1291 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
1292 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
1293 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
1294 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
1295 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
1296 };
1297
1298 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1299 fsl,pins =
1300 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
1301 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
1302 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
1303 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
1304 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
1305 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
1306 };
1307
1308 pinctrl_wdog: wdoggrp {
1309 fsl,pins =
1310 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */
1311 };
1312
1313 pinctrl_wifi_ctrl: wifictrlgrp {
1314 fsl,pins =
1315 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */
1316 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */
1317 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */
1318 };
1319
1320 pinctrl_wifi_i2s: bti2sgrp {
1321 fsl,pins =
1322 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */
1323 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */
1324 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */
1325 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */
1326 };
1327
1328 pinctrl_wifi_pwr_en: wifipwrengrp {
1329 fsl,pins =
1330 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */
1331 };
1332};