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git01.mediatek.com / filogic / uboot / d02ea501953103cf4ca969b923d01aa73d4ceb7d / . / drivers / ufs / cdns-platform.c
blob: 510a6a6aa5dd4702dfdd01712114931a5ba407e0 [file] [log] [blame]
Faiz Abbas204b2c22019-10-15 18:24:37 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/**
3 * cdns-platform.c - Platform driver for Cadence UFSHCI device
4 *
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame]5 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
Faiz Abbas204b2c22019-10-15 18:24:37 +0530[diff] [blame]6 */
7
8#include <clk.h>
Faiz Abbas204b2c22019-10-15 18:24:37 +0530[diff] [blame]9#include <dm.h>
10#include <ufs.h>
Simon Glass0b700eb2020-07-19 10:15:54 -0600[diff] [blame]11#include <asm/io.h>
Simon Glass9bc15642020-02-03 07:36:16 -0700[diff] [blame]12#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]13#include <linux/bitops.h>
Simon Glassd66c5f72020-02-03 07:36:15 -0700[diff] [blame]14#include <linux/err.h>
Igor Prusovc3421ea2023-11-09 20:10:04 +0300[diff] [blame]15#include <linux/time.h>
Faiz Abbas204b2c22019-10-15 18:24:37 +0530[diff] [blame]16
17#include "ufs.h"
18
Faiz Abbas204b2c22019-10-15 18:24:37 +0530[diff] [blame]19#define CDNS_UFS_REG_HCLKDIV 0xFC
20#define CDNS_UFS_REG_PHY_XCFGD1 0x113C
21
22static int cdns_ufs_link_startup_notify(struct ufs_hba *hba,
23 enum ufs_notify_change_status status)
24{
25 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
26 switch (status) {
27 case PRE_CHANGE:
28 return ufshcd_dme_set(hba,
29 UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
30 0);
31 case POST_CHANGE:
32 ;
33 }
34
35 return 0;
36}
37
38static int cdns_ufs_set_hclkdiv(struct ufs_hba *hba)
39{
40 struct clk clk;
41 unsigned long core_clk_rate = 0;
42 u32 core_clk_div = 0;
43 int ret;
44
45 ret = clk_get_by_name(hba->dev, "core_clk", &clk);
46 if (ret) {
47 dev_err(hba->dev, "failed to get core_clk clock\n");
48 return ret;
49 }
50
51 core_clk_rate = clk_get_rate(&clk);
52 if (IS_ERR_VALUE(core_clk_rate)) {
53 dev_err(hba->dev, "%s: unable to find core_clk rate\n",
54 __func__);
55 return core_clk_rate;
56 }
57
58 core_clk_div = core_clk_rate / USEC_PER_SEC;
59 ufshcd_writel(hba, core_clk_div, CDNS_UFS_REG_HCLKDIV);
60
61 return 0;
62}
63
64static int cdns_ufs_hce_enable_notify(struct ufs_hba *hba,
65 enum ufs_notify_change_status status)
66{
67 switch (status) {
68 case PRE_CHANGE:
69 return cdns_ufs_set_hclkdiv(hba);
70 case POST_CHANGE:
71 ;
72 }
73
74 return 0;
75}
76
77static int cdns_ufs_init(struct ufs_hba *hba)
78{
79 u32 data;
80
81 /* Increase RX_Advanced_Min_ActivateTime_Capability */
82 data = ufshcd_readl(hba, CDNS_UFS_REG_PHY_XCFGD1);
83 data |= BIT(24);
84 ufshcd_writel(hba, data, CDNS_UFS_REG_PHY_XCFGD1);
85
86 return 0;
87}
88
89static struct ufs_hba_ops cdns_pltfm_hba_ops = {
90 .init = cdns_ufs_init,
91 .hce_enable_notify = cdns_ufs_hce_enable_notify,
92 .link_startup_notify = cdns_ufs_link_startup_notify,
93};
94
95static int cdns_ufs_pltfm_probe(struct udevice *dev)
96{
97 int err = ufshcd_probe(dev, &cdns_pltfm_hba_ops);
98 if (err)
99 dev_err(dev, "ufshcd_probe() failed %d\n", err);
100
101 return err;
102}
103
104static int cdns_ufs_pltfm_bind(struct udevice *dev)
105{
106 struct udevice *scsi_dev;
107
108 return ufs_scsi_bind(dev, &scsi_dev);
109}
110
111static const struct udevice_id cdns_ufs_pltfm_ids[] = {
112 {
113 .compatible = "cdns,ufshc-m31-16nm",
114 },
115 {},
116};
117
118U_BOOT_DRIVER(cdns_ufs_pltfm) = {
119 .name = "cdns-ufs-pltfm",
Marek Vasut4533f052023-08-06 20:18:42 +0200[diff] [blame]120 .id = UCLASS_UFS,
Faiz Abbas204b2c22019-10-15 18:24:37 +0530[diff] [blame]121 .of_match = cdns_ufs_pltfm_ids,
122 .probe = cdns_ufs_pltfm_probe,
123 .bind = cdns_ufs_pltfm_bind,
124};