blob: f1600b2a3bda2d1c5d92ccc41de8e7f32acf9d5c [file] [log] [blame]
Mark Jonas35a398a2008-03-10 11:37:10 +01001/*
2 * Configuation settings for MPR2
3 *
4 * Copyright (C) 2008
5 * Mark Jonas <mark.jonas@de.bosch.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Mark Jonas35a398a2008-03-10 11:37:10 +01008 */
9
10#ifndef __MPR2_H
11#define __MPR2_H
12
13/* Supported commands */
Mark Jonas35a398a2008-03-10 11:37:10 +010014
15/* Default environment variables */
Joe Hershbergere4da2482011-10-13 13:03:48 +000016#define CONFIG_BOOTFILE "/boot/zImage"
Mark Jonas35a398a2008-03-10 11:37:10 +010017#define CONFIG_LOADADDR 0x8E000000
Mark Jonas35a398a2008-03-10 11:37:10 +010018
19/* CPU and platform */
Mark Jonas35a398a2008-03-10 11:37:10 +010020#define CONFIG_CPU_SH7720 1
Mark Jonas35a398a2008-03-10 11:37:10 +010021
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020022#define CONFIG_DISPLAY_BOARDINFO
23
Mark Jonas35a398a2008-03-10 11:37:10 +010024/* U-Boot internals */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020025#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
26#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
27#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
28#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
29#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Mark Jonas35a398a2008-03-10 11:37:10 +010030
31/* Memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020032#define CONFIG_SYS_SDRAM_BASE 0x8C000000
33#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
34#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
35#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Mark Jonas35a398a2008-03-10 11:37:10 +010036
37/* Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020038#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020039#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040#define CONFIG_SYS_FLASH_EMPTY_INFO
41#define CONFIG_SYS_FLASH_BASE 0xA0000000
42#define CONFIG_SYS_MAX_FLASH_SECT 256
43#define CONFIG_SYS_MAX_FLASH_BANKS 1
44#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020045#define CONFIG_ENV_SECT_SIZE (128 * 1024)
46#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020047#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
48#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
49#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Mark Jonas35a398a2008-03-10 11:37:10 +010050
51/* Clocks */
52#define CONFIG_SYS_CLK_FREQ 24000000
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090053#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
54#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +020055#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
Mark Jonas35a398a2008-03-10 11:37:10 +010056
57/* UART */
Mark Jonas35a398a2008-03-10 11:37:10 +010058#define CONFIG_CONS_SCIF0 1
59
60#endif /* __MPR2_H */