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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Marek Vasutc140e982011-11-08 23:18:08 +00002/*
Otavio Salvador5309b002012-08-05 09:05:30 +00003 * Freescale i.MXS Register Accessors
Marek Vasutc140e982011-11-08 23:18:08 +00004 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
Marek Vasutc140e982011-11-08 23:18:08 +00007 */
8
Otavio Salvador5309b002012-08-05 09:05:30 +00009#ifndef __MXS_REGS_COMMON_H__
10#define __MXS_REGS_COMMON_H__
Marek Vasutc140e982011-11-08 23:18:08 +000011
Peng Fan2728f832015-10-29 15:54:42 +080012#include <linux/types.h>
13
Marek Vasutc140e982011-11-08 23:18:08 +000014/*
Otavio Salvador5309b002012-08-05 09:05:30 +000015 * The i.MXS has interesting feature when it comes to register access. There
Marek Vasutc140e982011-11-08 23:18:08 +000016 * are four kinds of access to one particular register. Those are:
17 *
18 * 1) Common read/write access. To use this mode, just write to the address of
19 * the register.
20 * 2) Set bits only access. To set bits, write which bits you want to set to the
21 * address of the register + 0x4.
22 * 3) Clear bits only access. To clear bits, write which bits you want to clear
23 * to the address of the register + 0x8.
24 * 4) Toggle bits only access. To toggle bits, write which bits you want to
25 * toggle to the address of the register + 0xc.
26 *
27 * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
28 * can be set/cleared by pure write as in access type 1, some need to be
29 * explicitly set/cleared by using access type 2-3.
30 *
31 * The following macros and structures allow the user to either access the
32 * register in all aforementioned modes (by accessing reg_name, reg_name_set,
33 * reg_name_clr, reg_name_tog) or pass the register structure further into
34 * various functions with correct type information (by accessing reg_name_reg).
35 *
36 */
37
Otavio Salvador5309b002012-08-05 09:05:30 +000038#define __mxs_reg_8(name) \
Robert Deliene4d40fe2012-02-26 12:15:06 +000039 uint8_t name[4]; \
40 uint8_t name##_set[4]; \
41 uint8_t name##_clr[4]; \
42 uint8_t name##_tog[4]; \
43
Otavio Salvador5309b002012-08-05 09:05:30 +000044#define __mxs_reg_32(name) \
Marek Vasutc140e982011-11-08 23:18:08 +000045 uint32_t name; \
46 uint32_t name##_set; \
47 uint32_t name##_clr; \
48 uint32_t name##_tog;
49
Otavio Salvador5309b002012-08-05 09:05:30 +000050struct mxs_register_8 {
51 __mxs_reg_8(reg)
Robert Deliene4d40fe2012-02-26 12:15:06 +000052};
53
Otavio Salvador5309b002012-08-05 09:05:30 +000054struct mxs_register_32 {
55 __mxs_reg_32(reg)
Marek Vasutc140e982011-11-08 23:18:08 +000056};
57
Otavio Salvador5309b002012-08-05 09:05:30 +000058#define mxs_reg_8(name) \
Robert Deliene4d40fe2012-02-26 12:15:06 +000059 union { \
Otavio Salvador5309b002012-08-05 09:05:30 +000060 struct { __mxs_reg_8(name) }; \
61 struct mxs_register_8 name##_reg; \
Robert Deliene4d40fe2012-02-26 12:15:06 +000062 };
63
Otavio Salvador5309b002012-08-05 09:05:30 +000064#define mxs_reg_32(name) \
Marek Vasutc140e982011-11-08 23:18:08 +000065 union { \
Otavio Salvador5309b002012-08-05 09:05:30 +000066 struct { __mxs_reg_32(name) }; \
67 struct mxs_register_32 name##_reg; \
Marek Vasutc140e982011-11-08 23:18:08 +000068 };
69
Otavio Salvador5309b002012-08-05 09:05:30 +000070#endif /* __MXS_REGS_COMMON_H__ */