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Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -04001/*
2 * (C) Copyright 2008
Ricardo Ribalda Delgado5712d042016-01-26 11:24:08 +01003 * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -04004 * This work has been supported by: QTechnology http://qtec.com/
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -04007*/
8
9#include <config.h>
10#include <common.h>
Ricardo Ribalda Delgado3f355dd2016-01-26 13:47:45 +010011#include <netdev.h>
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040012#include <asm/processor.h>
13
Simon Glass39f90ba2017-03-31 08:40:25 -060014DECLARE_GLOBAL_DATA_PTR;
15
Ricardo Ribalda Delgado5db1f9d2016-01-26 11:24:21 +010016int checkboard(void)
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040017{
18 puts("Xilinx PPC440 Generic Board\n");
19 return 0;
20}
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040021
Simon Glassd35f3382017-04-06 12:47:05 -060022int dram_init(void)
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040023{
Simon Glass39f90ba2017-03-31 08:40:25 -060024 gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020025 CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
Simon Glass39f90ba2017-03-31 08:40:25 -060026
27 return 0;
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040028}
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040029
Ricardo Ribalda Delgado5db1f9d2016-01-26 11:24:21 +010030void get_sys_info(sys_info_t *sys_info)
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040031{
Ricardo Ribalda Delgado5db1f9d2016-01-26 11:24:21 +010032 sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
33 sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
34 sys_info->freqPCI = 0;
Ricardo Ribalda Delgadof84496a2008-09-01 13:09:39 -040035
36 return;
37}
Ricardo Ribalda Delgado4f40e132016-01-26 11:24:19 +010038
39int get_serial_clock(void){
40 return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
41}
Ricardo Ribalda Delgado3f355dd2016-01-26 13:47:45 +010042
43int board_eth_init(bd_t *bis)
44{
45 int ret = 0;
46
47 puts("Init xilinx temac\n");
48#ifdef XPAR_LLTEMAC_0_BASEADDR
49 ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR,
50 XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
51 XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR);
52
53#endif
54
55#ifdef XPAR_LLTEMAC_1_BASEADDR
56 ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR,
57 XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
58 XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR);
59#endif
60
61 return ret;
62}