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git01.mediatek.com / filogic / uboot / cfcf05efec7cb02661be6020c0682bdc26854e9f / . / arch / arm / dts / rk356x-u-boot.dtsi
blob: 05367216e118ad74d1f6cb6eff1b8eae0efeadb5 [file] [log] [blame]
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 */
5
Quentin Schulzd9ffa5e2022-09-02 15:10:52 +0200[diff] [blame]6#include "rockchip-u-boot.dtsi"
7
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]8/ {
9 aliases {
10 mmc0 = &sdhci;
11 mmc1 = &sdmmc0;
Jonas Karlmanaec644c2023-07-28 12:05:40 +0000[diff] [blame]12 spi4 = &sfc;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]13 };
14
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]15 chosen {
Jonas Karlmandab889e2023-07-28 11:53:08 +0000[diff] [blame]16 u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]17 };
18
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]19 dmc: dmc {
20 compatible = "rockchip,rk3568-dmc";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]22 };
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000[diff] [blame]23
Jonas Karlmancfcf05e2024-04-22 06:28:45 +0000[diff] [blame^]24 rng: rng@fe388000 {
25 compatible = "rockchip,cryptov2-rng";
26 reg = <0x0 0xfe388000 0x0 0x2000>;
27 };
28
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000[diff] [blame]29 otp: nvmem@fe38c000 {
30 compatible = "rockchip,rk3568-otp";
31 reg = <0x0 0xfe38c000 0x0 0x4000>;
32 #address-cells = <1>;
33 #size-cells = <1>;
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000[diff] [blame]34
35 cpu_id: id@a {
36 reg = <0x0a 0x10>;
37 };
38 };
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]39};
40
Jonas Karlman13e3dc92023-05-17 18:26:29 +0000[diff] [blame]41&xin24m {
42 bootph-all;
Jonas Karlman13e3dc92023-05-17 18:26:29 +0000[diff] [blame]43};
44
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]45&cru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]47};
48
49&pmucru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]51};
52
53&grf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]55};
56
57&pmugrf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]59};
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]60
Jonas Karlmanf216c612023-07-28 11:53:07 +0000[diff] [blame]61&pinctrl {
62 bootph-all;
63};
64
Jonas Karlmanc6391352023-08-03 21:11:54 +0000[diff] [blame]65&pcfg_pull_none_smt {
66 bootph-all;
67};
68
Jonas Karlmanf216c612023-07-28 11:53:07 +0000[diff] [blame]69&pcfg_pull_none {
70 bootph-all;
71};
72
73&pcfg_pull_up_drv_level_2 {
74 bootph-all;
75};
76
77&pcfg_pull_up {
78 bootph-all;
79};
80
81&emmc_bus8 {
82 bootph-all;
83};
84
85&emmc_clk {
86 bootph-all;
87};
88
89&emmc_cmd {
90 bootph-all;
91};
92
93&emmc_datastrobe {
94 bootph-all;
95};
96
97&emmc_rstnout {
98 bootph-all;
99};
100
101&fspi_pins {
102 bootph-all;
103};
104
Jonas Karlmanc6391352023-08-03 21:11:54 +0000[diff] [blame]105&i2c0_xfer {
106 bootph-all;
107};
108
Jonas Karlmanf216c612023-07-28 11:53:07 +0000[diff] [blame]109&sdmmc0_bus4 {
110 bootph-all;
111};
112
113&sdmmc0_clk {
114 bootph-all;
115};
116
117&sdmmc0_cmd {
118 bootph-all;
119};
120
121&sdmmc0_det {
122 bootph-all;
123};
124
125&sdmmc0_pwren {
126 bootph-all;
127};
128
129&uart2m0_xfer {
130 bootph-all;
131};
132
FUKAUMI Naoki98dc96a2022-10-04 01:30:30 +0000[diff] [blame]133&sdhci {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]134 bootph-pre-ram;
Jonas Karlmane8841382023-08-04 09:34:01 +0000[diff] [blame]135 max-frequency = <200000000>;
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]136};
137
FUKAUMI Naoki98dc96a2022-10-04 01:30:30 +0000[diff] [blame]138&sdmmc0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]139 bootph-pre-ram;
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]140};
Jonas Karlmana9d8d532023-05-17 18:26:35 +0000[diff] [blame]141
Jonas Karlman1fb8b8d2024-01-26 22:14:51 +0000[diff] [blame]142&uart2 {
143 bootph-pre-ram;
144 clock-frequency = <24000000>;
145};
146
Jonas Karlmana9d8d532023-05-17 18:26:35 +0000[diff] [blame]147#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
148&binman {
149 simple-bin-spi {
150 mkimage {
151 args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
152 offset = <0x8000>;
153 };
154 };
155};
156#endif