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git01.mediatek.com / filogic / uboot / cfa0e161e21bbd020509e70a1d43ba6d57c66290 / . / arch / arm / dts / stm32mp15xx-dhcor-u-boot.dtsi
blob: 552b35db3c7bf00ef824a1a3d8c2205276c44b46 [file] [log] [blame]
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2/*
3 * Copyright : STMicroelectronics 2018
4 *
5 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]7 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]8 */
9
10#include <dt-bindings/clock/stm32mp1-clksrc.h>
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]11#include "stm32mp15-u-boot.dtsi"
Marek Vasut272198e2020-04-29 15:08:38 +0200[diff] [blame]12#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
13#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
14#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]15
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]16/ {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-all;
Marek Vasut8b08dfb2021-12-30 23:46:46 +0100[diff] [blame]18
19 aliases {
20 eeprom0 = &eeprom0;
21 };
22
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]23 config {
Marek Vasut39221b52020-04-22 13:18:14 +0200[diff] [blame]24 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]25 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
26 };
27};
28
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]29&flash0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Patrick Delaunayf172bcb2023-06-08 17:16:48 +0200[diff] [blame]31
32 partitions {
33 compatible = "fixed-partitions";
34 #address-cells = <1>;
35 #size-cells = <1>;
36
37 partition@0 {
38 label = "fsbl1";
39 reg = <0x00000000 0x00040000>;
40 };
41 partition@40000 {
42 label = "fsbl2";
43 reg = <0x00040000 0x00040000>;
44 };
45 partition@500000 {
46 label = "uboot";
47 reg = <0x00080000 0x00160000>;
48 };
49 partition@900000 {
50 label = "env1";
51 reg = <0x001E0000 0x00010000>;
52 };
53 partition@980000 {
54 label = "env2";
55 reg = <0x001F0000 0x00010000>;
56 };
57 };
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]58};
59
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]60&i2c4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-all;
62 bootph-pre-ram;
Marek Vasut8b08dfb2021-12-30 23:46:46 +0100[diff] [blame]63
64 eeprom0: eeprom@53 {
65 };
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]66};
67
68&i2c4_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]70 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]72 };
73};
74
75&pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-all;
77 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]78
79 regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]81 };
82};
83
84&pwr_regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]86};
87
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]88&qspi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]90};
91
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]92&qspi_clk_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]94 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]96 };
97};
98
99&qspi_bk1_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Marek Vasut3f3375c2023-10-10 01:15:51 +0200[diff] [blame]101 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]103 };
Marek Vasut3f3375c2023-10-10 01:15:51 +0200[diff] [blame]104};
105
106&qspi_cs1_pins_a {
107 bootph-pre-ram;
108 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]110 };
111};
112
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]113&rcc {
114 st,clksrc = <
115 CLK_MPU_PLL1P
116 CLK_AXI_PLL2P
117 CLK_MCU_PLL3P
118 CLK_PLL12_HSE
119 CLK_PLL3_HSE
120 CLK_PLL4_HSE
121 CLK_RTC_LSE
122 CLK_MCO1_DISABLED
123 CLK_MCO2_DISABLED
124 >;
125
126 st,clkdiv = <
127 1 /*MPU*/
128 0 /*AXI*/
129 0 /*MCU*/
130 1 /*APB1*/
131 1 /*APB2*/
132 1 /*APB3*/
133 1 /*APB4*/
134 2 /*APB5*/
135 23 /*RTC*/
136 0 /*MCO1*/
137 0 /*MCO2*/
138 >;
139
140 st,pkcs = <
141 CLK_CKPER_HSE
142 CLK_FMC_ACLK
143 CLK_QSPI_ACLK
144 CLK_ETH_DISABLED
145 CLK_SDMMC12_PLL4P
146 CLK_DSI_DSIPLL
147 CLK_STGEN_HSE
148 CLK_USBPHY_HSE
149 CLK_SPI2S1_PLL3Q
150 CLK_SPI2S23_PLL3Q
151 CLK_SPI45_HSI
152 CLK_SPI6_HSI
153 CLK_I2C46_HSI
154 CLK_SDMMC3_PLL4P
155 CLK_USBO_USBPHY
156 CLK_ADC_CKPER
157 CLK_CEC_LSE
158 CLK_I2C12_HSI
159 CLK_I2C35_HSI
160 CLK_UART1_HSI
161 CLK_UART24_HSI
162 CLK_UART35_HSI
163 CLK_UART6_HSI
164 CLK_UART78_HSI
165 CLK_SPDIF_PLL4P
Antonio Borneo84159e82020-01-28 10:11:01 +0100[diff] [blame]166 CLK_FDCAN_PLL4R
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]167 CLK_SAI1_PLL3Q
168 CLK_SAI2_PLL3Q
169 CLK_SAI3_PLL3Q
170 CLK_SAI4_PLL3Q
171 CLK_RNG1_LSI
172 CLK_RNG2_LSI
173 CLK_LPTIM1_PCLK1
174 CLK_LPTIM23_PCLK3
175 CLK_LPTIM45_LSE
176 >;
177
Marek Vasut086fa932022-10-11 22:42:44 +0200[diff] [blame]178 /*
179 * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
180 * frac = < f >;
181 *
182 * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
183 * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
184 * m ... for PLL1,2: m=2 ; for PLL3,4: m=1
185 * XTAL = 24 MHz
186 *
187 * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
188 * P = VCO / (P + 1)
189 * Q = VCO / (Q + 1)
190 * R = VCO / (R + 1)
191 */
192
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]193 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
194 pll2: st,pll@1 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]195 compatible = "st,stm32mp1-pll";
196 reg = <1>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]197 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
198 frac = < 0x1400 >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]199 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]200 };
201
202 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
203 pll3: st,pll@2 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]204 compatible = "st,stm32mp1-pll";
205 reg = <2>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]206 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
207 frac = < 0x1a04 >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]208 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]209 };
210
Marek Vasut086fa932022-10-11 22:42:44 +0200[diff] [blame]211 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]212 pll4: st,pll@3 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]213 compatible = "st,stm32mp1-pll";
214 reg = <3>;
Marek Vasutb48223e2020-08-22 22:45:25 +0200[diff] [blame]215 cfg = < 3 98 5 7 5 PQR(1,1,1) >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]216 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]217 };
218};
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]219
220&reg11 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]221 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]222};
223
224&reg18 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]225 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]226};
227
Marek Vasut5c92da92022-01-28 19:35:20 +0100[diff] [blame]228&usb33 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]229 bootph-pre-ram;
Marek Vasut5c92da92022-01-28 19:35:20 +0100[diff] [blame]230};
231
232&usbotg_hs_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]233 bootph-pre-ram;
Marek Vasut5c92da92022-01-28 19:35:20 +0100[diff] [blame]234};
235
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]236&usbotg_hs {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]237 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]238};
239
240&usbphyc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]241 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]242};
243
244&usbphyc_port0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]245 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]246};
247
248&usbphyc_port1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]249 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]250};
251
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]252&vdd_usb {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]253 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]254};