blob: 639a30a310e305c667334f2e816dc8e6996bd73e [file] [log] [blame]
Linus Walleij717b0a82012-08-04 05:21:28 +00001/*
2 * (C) Copyright 2012
3 * Linaro
4 * Linus Walleij <linus.walleij@linaro.org>
5 * Common ARM Integrator configuration settings
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Linus Walleij717b0a82012-08-04 05:21:28 +00008 */
9
Linus Walleij717b0a82012-08-04 05:21:28 +000010#define CONFIG_SYS_TEXT_BASE 0x01000000
11#define CONFIG_SYS_MEMTEST_START 0x100000
12#define CONFIG_SYS_MEMTEST_END 0x10000000
Linus Walleij717b0a82012-08-04 05:21:28 +000013#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */
14#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
15#define CONFIG_SYS_LONGHELP
16#define CONFIG_SYS_HUSH_PARSER
17#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
18#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
19#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
20#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/
21#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */
22
Linus Walleij616d9a02015-07-27 11:22:48 +020023/* Serial port PL010/PL011 through the device model */
24#define CONFIG_PL01X_SERIAL
25#define CONFIG_BAUDRATE 38400
26#define CONFIG_CONS_INDEX 0
27
Linus Walleij717b0a82012-08-04 05:21:28 +000028#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
29#define CONFIG_SETUP_MEMORY_TAGS
Linus Walleij44796de2013-04-03 19:19:20 +000030#define CONFIG_OF_LIBFDT /* enable passing a Device Tree */
Linus Walleij717b0a82012-08-04 05:21:28 +000031#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */
Linus Walleij717b0a82012-08-04 05:21:28 +000032
33/*
34 * There are various dependencies on the core module (CM) fitted
35 * Users should refer to their CM user guide
36 */
37#include "armcoremodule.h"
38
39/*
40 * Initialize and remap the core module, use SPD to detect memory size
41 * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
42 * the core module has a CM_INIT register
43 * then the U-Boot initialisation code will
44 * e.g. ARM Boot Monitor or pre-loader is repeated once
45 * (to re-initialise any existing CM_INIT settings to safe values).
46 *
47 * This is usually not the desired behaviour since the platform
48 * will either reboot into the ARM monitor (or pre-loader)
49 * or continuously cycle thru it without U-Boot running,
50 * depending upon the setting of Integrator/CP switch S2-4.
51 *
52 * However it may be needed if Integrator/CP switch S2-1
53 * is set OFF to boot direct into U-Boot.
54 * In that case comment out the line below.
55 */
56#define CONFIG_CM_INIT
57#define CONFIG_CM_REMAP
58#define CONFIG_CM_SPD_DETECT
59
60/*
61 * The ARM boot monitor initializes the board.
62 * However, the default U-Boot code also performs the initialization.
63 * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
64 * - see documentation supplied with board for details of how to choose the
65 * image to run at reset/power up
66 * e.g. whether the ARM Boot Monitor runs before U-Boot
67 */
68/* #define CONFIG_SKIP_LOWLEVEL_INIT */
69
70/*
71 * The ARM boot monitor does not relocate U-Boot.
72 * However, the default U-Boot code performs the relocation check,
73 * and may relocate the code if the memory map is changed.
74 * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
75 */
76/* #define SKIP_CONFIG_RELOCATE_UBOOT */
77
78
79/*
80 * Physical Memory Map
81 */
82#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
83#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
84#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
85#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
86#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
87#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
88 CONFIG_SYS_INIT_RAM_SIZE - \
89 GENERATED_GBL_DATA_SIZE)
90#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
Linus Walleij48fd6152015-04-05 01:48:33 +020091
92/*
93 * FLASH and environment organization
94 * Top varies according to amount fitted
95 * Reserve top 4 blocks of flash
96 * - ARM Boot Monitor
97 * - Unused
98 * - SIB block
99 * - U-Boot environment
100 */
Linus Walleij48fd6152015-04-05 01:48:33 +0200101#define CONFIG_CMD_ARMFLASH
102#define CONFIG_SYS_FLASH_CFI 1
103#define CONFIG_FLASH_CFI_DRIVER 1
104#define CONFIG_SYS_FLASH_BASE 0x24000000
105#define CONFIG_SYS_MAX_FLASH_BANKS 1
106
107/* Timeout values in ticks */
108#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
109#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
110#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
111#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */