Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Nobuhiro Iwamatsu | 4a495bc | 2013-11-21 17:07:45 +0900 | [diff] [blame] | 2 | /* |
| 3 | * arch/arm/include/asm/arch-rmobile/r8a7791.h |
Nobuhiro Iwamatsu | 4a495bc | 2013-11-21 17:07:45 +0900 | [diff] [blame] | 4 | * |
Nobuhiro Iwamatsu | 52b9674 | 2014-03-27 16:11:17 +0900 | [diff] [blame] | 5 | * Copyright (C) 2013,2014 Renesas Electronics Corporation |
Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 6 | */ |
Nobuhiro Iwamatsu | 4a495bc | 2013-11-21 17:07:45 +0900 | [diff] [blame] | 7 | |
| 8 | #ifndef __ASM_ARCH_R8A7791_H |
| 9 | #define __ASM_ARCH_R8A7791_H |
| 10 | |
Nobuhiro Iwamatsu | 52b9674 | 2014-03-27 16:11:17 +0900 | [diff] [blame] | 11 | #include "rcar-base.h" |
Nobuhiro Iwamatsu | 4a495bc | 2013-11-21 17:07:45 +0900 | [diff] [blame] | 12 | /* |
Nobuhiro Iwamatsu | 52b9674 | 2014-03-27 16:11:17 +0900 | [diff] [blame] | 13 | * R-Car (R8A7791) I/O Addresses |
Nobuhiro Iwamatsu | 4a495bc | 2013-11-21 17:07:45 +0900 | [diff] [blame] | 14 | */ |
Nobuhiro Iwamatsu | dc2c4f0 | 2014-11-06 16:03:47 +0900 | [diff] [blame] | 15 | |
Nobuhiro Iwamatsu | 3ec5f86 | 2014-12-17 08:03:00 +0900 | [diff] [blame] | 16 | /* SDHI */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 17 | #define CFG_SYS_SH_SDHI_NR_CHANNEL 3 |
Nobuhiro Iwamatsu | 3ec5f86 | 2014-12-17 08:03:00 +0900 | [diff] [blame] | 18 | |
Nobuhiro Iwamatsu | 7fbb92b | 2013-11-21 17:07:46 +0900 | [diff] [blame] | 19 | #define DBSC3_1_QOS_R0_BASE 0xE67A1000 |
| 20 | #define DBSC3_1_QOS_R1_BASE 0xE67A1100 |
| 21 | #define DBSC3_1_QOS_R2_BASE 0xE67A1200 |
| 22 | #define DBSC3_1_QOS_R3_BASE 0xE67A1300 |
| 23 | #define DBSC3_1_QOS_R4_BASE 0xE67A1400 |
| 24 | #define DBSC3_1_QOS_R5_BASE 0xE67A1500 |
| 25 | #define DBSC3_1_QOS_R6_BASE 0xE67A1600 |
| 26 | #define DBSC3_1_QOS_R7_BASE 0xE67A1700 |
| 27 | #define DBSC3_1_QOS_R8_BASE 0xE67A1800 |
| 28 | #define DBSC3_1_QOS_R9_BASE 0xE67A1900 |
| 29 | #define DBSC3_1_QOS_R10_BASE 0xE67A1A00 |
| 30 | #define DBSC3_1_QOS_R11_BASE 0xE67A1B00 |
| 31 | #define DBSC3_1_QOS_R12_BASE 0xE67A1C00 |
| 32 | #define DBSC3_1_QOS_R13_BASE 0xE67A1D00 |
| 33 | #define DBSC3_1_QOS_R14_BASE 0xE67A1E00 |
| 34 | #define DBSC3_1_QOS_R15_BASE 0xE67A1F00 |
| 35 | #define DBSC3_1_QOS_W0_BASE 0xE67A2000 |
| 36 | #define DBSC3_1_QOS_W1_BASE 0xE67A2100 |
| 37 | #define DBSC3_1_QOS_W2_BASE 0xE67A2200 |
| 38 | #define DBSC3_1_QOS_W3_BASE 0xE67A2300 |
| 39 | #define DBSC3_1_QOS_W4_BASE 0xE67A2400 |
| 40 | #define DBSC3_1_QOS_W5_BASE 0xE67A2500 |
| 41 | #define DBSC3_1_QOS_W6_BASE 0xE67A2600 |
| 42 | #define DBSC3_1_QOS_W7_BASE 0xE67A2700 |
| 43 | #define DBSC3_1_QOS_W8_BASE 0xE67A2800 |
| 44 | #define DBSC3_1_QOS_W9_BASE 0xE67A2900 |
| 45 | #define DBSC3_1_QOS_W10_BASE 0xE67A2A00 |
| 46 | #define DBSC3_1_QOS_W11_BASE 0xE67A2B00 |
| 47 | #define DBSC3_1_QOS_W12_BASE 0xE67A2C00 |
| 48 | #define DBSC3_1_QOS_W13_BASE 0xE67A2D00 |
| 49 | #define DBSC3_1_QOS_W14_BASE 0xE67A2E00 |
| 50 | #define DBSC3_1_QOS_W15_BASE 0xE67A2F00 |
Nobuhiro Iwamatsu | 747a3ad | 2014-05-19 12:23:35 +0900 | [diff] [blame] | 51 | #define DBSC3_1_DBADJ2 0xE67A00C8 |
Nobuhiro Iwamatsu | 7fbb92b | 2013-11-21 17:07:46 +0900 | [diff] [blame] | 52 | |
Nobuhiro Iwamatsu | 5f4d280 | 2014-12-02 16:52:22 +0900 | [diff] [blame] | 53 | /* Module stop control/status register bits */ |
| 54 | #define MSTP0_BITS 0x00640801 |
| 55 | #define MSTP1_BITS 0x9B6C9B5A |
| 56 | #define MSTP2_BITS 0x100D21FC |
| 57 | #define MSTP3_BITS 0xF08CD810 |
| 58 | #define MSTP4_BITS 0x800001C4 |
| 59 | #define MSTP5_BITS 0x44C00046 |
| 60 | #define MSTP7_BITS 0x05BFE618 |
| 61 | #define MSTP8_BITS 0x40C0FE85 |
| 62 | #define MSTP9_BITS 0xFF979FFF |
| 63 | #define MSTP10_BITS 0xFFFEFFE0 |
| 64 | #define MSTP11_BITS 0x000001C0 |
| 65 | |
Nobuhiro Iwamatsu | dc7ef50 | 2014-03-28 13:43:40 +0900 | [diff] [blame] | 66 | #define R8A7791_CUT_ES2X 2 |
| 67 | #define IS_R8A7791_ES2() \ |
| 68 | (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X) |
| 69 | |
Nobuhiro Iwamatsu | 4a495bc | 2013-11-21 17:07:45 +0900 | [diff] [blame] | 70 | #endif /* __ASM_ARCH_R8A7791_H */ |