| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcom MPM Interrupt Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Shawn Guo <shawn.guo@linaro.org> |
| 11 | |
| 12 | description: |
| 13 | Qualcomm Technologies Inc. SoCs based on the RPM architecture have a |
| 14 | MSM Power Manager (MPM) that is in always-on domain. In addition to managing |
| 15 | resources during sleep, the hardware also has an interrupt controller that |
| 16 | monitors the interrupts when the system is asleep, wakes up the APSS when |
| 17 | one of these interrupts occur and replays it to GIC interrupt controller |
| 18 | after GIC becomes operational. |
| 19 | |
| 20 | allOf: |
| 21 | - $ref: /schemas/interrupt-controller.yaml# |
| 22 | |
| 23 | properties: |
| 24 | compatible: |
| 25 | items: |
| 26 | - const: qcom,mpm |
| 27 | |
| 28 | reg: |
| 29 | maxItems: 1 |
| 30 | description: |
| 31 | Specifies the base address and size of vMPM registers in RPM MSG RAM. |
| 32 | |
| 33 | interrupts: |
| 34 | maxItems: 1 |
| 35 | description: |
| 36 | Specify the IRQ used by RPM to wakeup APSS. |
| 37 | |
| 38 | mboxes: |
| 39 | maxItems: 1 |
| 40 | description: |
| 41 | Specify the mailbox used to notify RPM for writing vMPM registers. |
| 42 | |
| 43 | interrupt-controller: true |
| 44 | |
| 45 | '#interrupt-cells': |
| 46 | const: 2 |
| 47 | description: |
| 48 | The first cell is the MPM pin number for the interrupt, and the second |
| 49 | is the trigger type. |
| 50 | |
| 51 | qcom,mpm-pin-count: |
| 52 | description: |
| 53 | Specify the total MPM pin count that a SoC supports. |
| 54 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 55 | |
| 56 | qcom,mpm-pin-map: |
| 57 | description: |
| 58 | A set of MPM pin numbers and the corresponding GIC SPIs. |
| 59 | $ref: /schemas/types.yaml#/definitions/uint32-matrix |
| 60 | items: |
| 61 | items: |
| 62 | - description: MPM pin number |
| 63 | - description: GIC SPI number for the MPM pin |
| 64 | |
| 65 | '#power-domain-cells': |
| 66 | const: 0 |
| 67 | |
| 68 | required: |
| 69 | - compatible |
| 70 | - reg |
| 71 | - interrupts |
| 72 | - mboxes |
| 73 | - interrupt-controller |
| 74 | - '#interrupt-cells' |
| 75 | - qcom,mpm-pin-count |
| 76 | - qcom,mpm-pin-map |
| 77 | |
| 78 | additionalProperties: false |
| 79 | |
| 80 | examples: |
| 81 | - | |
| 82 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 83 | mpm: interrupt-controller@45f01b8 { |
| 84 | compatible = "qcom,mpm"; |
| 85 | interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; |
| 86 | reg = <0x45f01b8 0x1000>; |
| 87 | mboxes = <&apcs_glb 1>; |
| 88 | interrupt-controller; |
| 89 | #interrupt-cells = <2>; |
| 90 | interrupt-parent = <&intc>; |
| 91 | qcom,mpm-pin-count = <96>; |
| 92 | qcom,mpm-pin-map = <2 275>, |
| 93 | <5 296>, |
| 94 | <12 422>, |
| 95 | <24 79>, |
| 96 | <86 183>, |
| 97 | <90 260>, |
| 98 | <91 260>; |
| 99 | #power-domain-cells = <0>; |
| 100 | }; |