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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Wolfgang Wegner406471c2010-01-25 11:27:44 +01002/*
3 * Configuration settings for the Sentec Cobra Board.
4 *
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
Wolfgang Wegner406471c2010-01-25 11:27:44 +01006 */
7
8/*
9 * configuration for ASTRO "Urmel" board.
10 * Originating from Cobra5272 configuration, messed up by
11 * Wolfgang Wegner <w.wegner@astro-kom.de>
12 * Please do not bother the original author with bug reports
13 * concerning this file.
14 */
15
16#ifndef _CONFIG_ASTRO_MCF5373L_H
17#define _CONFIG_ASTRO_MCF5373L_H
18
Marek Vasut1b476f92012-09-23 17:41:25 +020019#include <linux/stringify.h>
20
Wolfgang Wegner406471c2010-01-25 11:27:44 +010021/*
22 * set the card type to actually compile for; either of
23 * the possibilities listed below has to be used!
24 */
Tom Rinie8eb04a2021-08-19 15:16:15 -040025#define ASTRO_V532 1
Wolfgang Wegner406471c2010-01-25 11:27:44 +010026
Tom Rinie8eb04a2021-08-19 15:16:15 -040027#if ASTRO_V532
Wolfgang Wegner406471c2010-01-25 11:27:44 +010028#define ASTRO_ID 0xF8
Tom Rinie8eb04a2021-08-19 15:16:15 -040029#elif ASTRO_V512
Wolfgang Wegner406471c2010-01-25 11:27:44 +010030#define ASTRO_ID 0xFA
Tom Rinie8eb04a2021-08-19 15:16:15 -040031#elif ASTRO_TWIN7S2
Wolfgang Wegner406471c2010-01-25 11:27:44 +010032#define ASTRO_ID 0xF9
Tom Rinie8eb04a2021-08-19 15:16:15 -040033#elif ASTRO_V912
Wolfgang Wegner406471c2010-01-25 11:27:44 +010034#define ASTRO_ID 0xFC
Tom Rinie8eb04a2021-08-19 15:16:15 -040035#elif ASTRO_COFDMDUOS2
Wolfgang Wegner406471c2010-01-25 11:27:44 +010036#define ASTRO_ID 0xFB
37#else
38#error No card type defined!
39#endif
40
Wolfgang Wegner406471c2010-01-25 11:27:44 +010041/* I2C */
Wolfgang Wegner406471c2010-01-25 11:27:44 +010042
43/*
44 * Defines processor clock - important for correct timings concerning serial
45 * interface etc.
Wolfgang Wegner406471c2010-01-25 11:27:44 +010046 */
47
Tom Rini6a5dccc2022-11-16 13:10:41 -050048#define CFG_SYS_CLK 80000000
49#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 3)
Tom Rinibb4dd962022-11-16 13:10:37 -050050#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
Wolfgang Wegner406471c2010-01-25 11:27:44 +010051
Wolfgang Wegner406471c2010-01-25 11:27:44 +010052/*
53 * Define baudrate for UART1 (console output, tftp, ...)
54 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Tom Rini6a5dccc2022-11-16 13:10:41 -050055 * CFG_SYS_BAUDRATE_TABLE defines values that can be selected
Wolfgang Wegner406471c2010-01-25 11:27:44 +010056 * in u-boot command interface
57 */
58
Tom Rini6a5dccc2022-11-16 13:10:41 -050059#define CFG_SYS_UART_PORT (2)
60#define CFG_SYS_UART2_ALT3_GPIO
Wolfgang Wegner406471c2010-01-25 11:27:44 +010061
Wolfgang Wegner406471c2010-01-25 11:27:44 +010062/* here we put our FPGA configuration... */
Wolfgang Wegner406471c2010-01-25 11:27:44 +010063
64/* Define user parameters that have to be customized most likely */
65
66/* AUTOBOOT settings - booting images automatically by u-boot after power on */
67
68/*
Wolfgang Wegner406471c2010-01-25 11:27:44 +010069 * The following settings will be contained in the environment block ; if you
70 * want to use a neutral environment all those settings can be manually set in
71 * u-boot: 'set' command
72 */
73
Tom Rinic9edebe2022-12-04 10:03:50 -050074#define CFG_EXTRA_ENV_SETTINGS \
Wolfgang Wegner406471c2010-01-25 11:27:44 +010075 "loaderversion=11\0" \
Marek Vasut1b476f92012-09-23 17:41:25 +020076 "card_id="__stringify(ASTRO_ID)"\0" \
Wolfgang Wegner406471c2010-01-25 11:27:44 +010077 "alterafile=0\0" \
78 "xilinxfile=0\0" \
79 "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
80 "fpga load 0 0x41000000 $filesize\0" \
81 "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\
82 "fpga load 1 0x41000000 $filesize\0" \
83 "env_default=1\0" \
84 "env_check=if test $env_default -eq 1;"\
85 " then setenv env_default 0;saveenv;fi\0"
86
87/*
88 * "update" is a non-standard command that has to be supplied
89 * by external update.c; This is not included in mainline because
90 * it needs non-blocking CFI routines.
91 */
Wolfgang Wegner406471c2010-01-25 11:27:44 +010092
Tom Rini6a5dccc2022-11-16 13:10:41 -050093#define CFG_SYS_FPGA_WAIT 1000
Wolfgang Wegner406471c2010-01-25 11:27:44 +010094
95/* End of user parameters to be customized */
96
97/* Defines memory range for test */
98
Wolfgang Wegner406471c2010-01-25 11:27:44 +010099/*
100 * Low Level Configuration Settings
101 * (address mappings, register initial values, etc.)
102 * You should know what you are doing if you make changes here.
103 */
104
105/* Base register address */
106
Tom Rini6a5dccc2022-11-16 13:10:41 -0500107#define CFG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100108
109/* System Conf. Reg. & System Protection Reg. */
110
Tom Rini6a5dccc2022-11-16 13:10:41 -0500111#define CFG_SYS_SCR 0x0003;
112#define CFG_SYS_SPR 0xffff;
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100113
114/*
115 * Definitions for initial stack pointer and data area (in internal SRAM)
116 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500117#define CFG_SYS_INIT_RAM_ADDR 0x80000000
118#define CFG_SYS_INIT_RAM_SIZE 0x8000
119#define CFG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100120
121/*
122 * Start addresses for the final memory configuration
123 * (Set up by the startup code)
124 * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
125 */
Tom Rinibb4dd962022-11-16 13:10:37 -0500126#define CFG_SYS_SDRAM_BASE 0x40000000
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100127
128/*
129 * Chipselect bank definitions
130 *
131 * CS0 - Flash 32MB (first 16MB)
132 * CS1 - Flash 32MB (second half)
133 * CS2 - FPGA
134 * CS3 - FPGA
135 * CS4 - unused
136 * CS5 - unused
137 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500138#define CFG_SYS_CS0_BASE 0
139#define CFG_SYS_CS0_MASK 0x00ff0001
140#define CFG_SYS_CS0_CTRL 0x00001fc0
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100141
Tom Rini6a5dccc2022-11-16 13:10:41 -0500142#define CFG_SYS_CS1_BASE 0x01000000
143#define CFG_SYS_CS1_MASK 0x00ff0001
144#define CFG_SYS_CS1_CTRL 0x00001fc0
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100145
Tom Rini6a5dccc2022-11-16 13:10:41 -0500146#define CFG_SYS_CS2_BASE 0x20000000
147#define CFG_SYS_CS2_MASK 0x00ff0001
148#define CFG_SYS_CS2_CTRL 0x0000fec0
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100149
Tom Rini6a5dccc2022-11-16 13:10:41 -0500150#define CFG_SYS_CS3_BASE 0x21000000
151#define CFG_SYS_CS3_MASK 0x00ff0001
152#define CFG_SYS_CS3_CTRL 0x0000fec0
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100153
Tom Rini6a5dccc2022-11-16 13:10:41 -0500154#define CFG_SYS_FLASH_BASE 0x00000000
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100155
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100156/* Reserve 256 kB for Monitor */
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100157
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100158/*
159 * For booting Linux, the board info and command line data
160 * have to be in the first 8 MB of memory, since this is
161 * the maximum mapped by the Linux kernel during initialization ??
162 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500163#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
Tom Rinibb4dd962022-11-16 13:10:37 -0500164 (CFG_SYS_SDRAM_SIZE << 20))
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100165
166/* FLASH organization */
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100167
Tom Rini6a5dccc2022-11-16 13:10:41 -0500168#define CFG_SYS_FLASH_SIZE 0x2000000
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100169
angelo@sysam.it6312a952015-03-29 22:54:16 +0200170#define LDS_BOARD_TEXT \
171 . = DEFINED(env_offset) ? env_offset : .; \
Simon Glass547cb402017-08-03 12:21:49 -0600172 env/embedded.o(.text*)
angelo@sysam.it6312a952015-03-29 22:54:16 +0200173
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100174/* Cache Configuration */
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100175
Tom Rini6a5dccc2022-11-16 13:10:41 -0500176#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
177 CFG_SYS_INIT_RAM_SIZE - 8)
178#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
179 CFG_SYS_INIT_RAM_SIZE - 4)
180#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
181#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
Tom Rinibb4dd962022-11-16 13:10:37 -0500182 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600183 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500184#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600185 CF_CACR_DCM_P)
186
Angelo Dureghello49becce2023-02-25 23:25:26 +0100187#define CFG_MCFTMR
188
Wolfgang Wegner406471c2010-01-25 11:27:44 +0100189#endif /* _CONFIG_ASTRO_MCF5373L_H */