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git01.mediatek.com / filogic / uboot / cf3cd803c614e1890bc4a9f00fc0928b652b3a66 / . / arch / arm / dts / zynqmp-zcu102-revA.dts
blob: 3132fa533b8ed0625ea47fbe6fe5ad0cb3c9eaa4 [file] [log] [blame]
Michal Simek090a2d72018-03-27 10:36:39 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]2/*
Michal Simek0bfbb212017-11-02 10:21:08 +0100[diff] [blame]3 * dts file for Xilinx ZynqMP ZCU102 RevA
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]4 *
Michal Simek3f283ea2023-09-22 12:35:41 +0200[diff] [blame]5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]7 *
Michal Simeka8c94362023-07-10 14:35:49 +0200[diff] [blame]8 * Michal Simek <michal.simek@amd.com>
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
Michal Simeka6604b62017-12-08 14:50:42 +0100[diff] [blame]14#include "zynqmp-clk-ccf.dtsi"
Michal Simekc87c7b22018-03-27 12:13:13 +0200[diff] [blame]15#include <dt-bindings/input/input.h>
Michal Simek7df37832016-05-25 20:09:35 +0200[diff] [blame]16#include <dt-bindings/gpio/gpio.h>
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]17#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
Michal Simekd5ba4f22017-12-01 15:50:31 +0100[diff] [blame]18#include <dt-bindings/phy/phy.h>
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]19
20/ {
21 model = "ZynqMP ZCU102 RevA";
Michal Simek40d839a2017-07-20 12:38:27 +0200[diff] [blame]22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]23
24 aliases {
25 ethernet0 = &gem3;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 mmc0 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +0200[diff] [blame]29 nvmem0 = &eeprom;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]30 rtc0 = &rtc;
31 serial0 = &uart0;
32 serial1 = &uart1;
Michal Simekde29d542016-09-09 08:46:39 +0200[diff] [blame]33 serial2 = &dcc;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]34 spi0 = &qspi;
35 usb0 = &usb0;
36 };
37
38 chosen {
39 bootargs = "earlycon";
40 stdout-path = "serial0:115200n8";
41 };
42
Michal Simek79c1cbf2016-11-11 13:21:04 +0100[diff] [blame]43 memory@0 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]44 device_type = "memory";
45 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
46 };
Michal Simekbe3c95f2016-04-20 13:12:25 +0200[diff] [blame]47
Michal Simek7df37832016-05-25 20:09:35 +0200[diff] [blame]48 gpio-keys {
49 compatible = "gpio-keys";
Michal Simek7df37832016-05-25 20:09:35 +0200[diff] [blame]50 autorepeat;
Michal Simek192d4ae2022-12-09 13:56:40 +0100[diff] [blame]51 switch-19 {
Michal Simek7df37832016-05-25 20:09:35 +0200[diff] [blame]52 label = "sw19";
53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
Michal Simekc87c7b22018-03-27 12:13:13 +0200[diff] [blame]54 linux,code = <KEY_DOWN>;
Sudeep Holla13104ce2018-10-24 12:45:40 +0100[diff] [blame]55 wakeup-source;
Michal Simek7df37832016-05-25 20:09:35 +0200[diff] [blame]56 autorepeat;
57 };
58 };
59
Michal Simekbe3c95f2016-04-20 13:12:25 +0200[diff] [blame]60 leds {
61 compatible = "gpio-leds";
Michal Simek2ef53362018-11-08 10:06:53 +0100[diff] [blame]62 heartbeat-led {
Michal Simekbe3c95f2016-04-20 13:12:25 +0200[diff] [blame]63 label = "heartbeat";
Chirag Parekhcc406a62017-01-25 07:00:57 -0800[diff] [blame]64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
Michal Simekbe3c95f2016-04-20 13:12:25 +0200[diff] [blame]65 linux,default-trigger = "heartbeat";
66 };
67 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]68
69 ina226-u76 {
70 compatible = "iio-hwmon";
71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
72 };
73 ina226-u77 {
74 compatible = "iio-hwmon";
75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
76 };
77 ina226-u78 {
78 compatible = "iio-hwmon";
79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
80 };
81 ina226-u87 {
82 compatible = "iio-hwmon";
83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
84 };
85 ina226-u85 {
86 compatible = "iio-hwmon";
87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
88 };
89 ina226-u86 {
90 compatible = "iio-hwmon";
91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
92 };
93 ina226-u93 {
94 compatible = "iio-hwmon";
95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
96 };
97 ina226-u88 {
98 compatible = "iio-hwmon";
99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
100 };
101 ina226-u15 {
102 compatible = "iio-hwmon";
103 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
104 };
105 ina226-u92 {
106 compatible = "iio-hwmon";
107 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
108 };
109 ina226-u79 {
110 compatible = "iio-hwmon";
111 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
112 };
113 ina226-u81 {
114 compatible = "iio-hwmon";
115 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
116 };
117 ina226-u80 {
118 compatible = "iio-hwmon";
119 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
120 };
121 ina226-u84 {
122 compatible = "iio-hwmon";
123 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
124 };
125 ina226-u16 {
126 compatible = "iio-hwmon";
127 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
128 };
129 ina226-u65 {
130 compatible = "iio-hwmon";
131 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
132 };
133 ina226-u74 {
134 compatible = "iio-hwmon";
135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
136 };
137 ina226-u75 {
138 compatible = "iio-hwmon";
139 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
140 };
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]141
142 /* 48MHz reference crystal */
143 ref48: ref48M {
144 compatible = "fixed-clock";
145 #clock-cells = <0>;
146 clock-frequency = <48000000>;
147 };
148
149 refhdmi: refhdmi {
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
152 clock-frequency = <114285000>;
153 };
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]154};
155
156&can1 {
157 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_can1_default>;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]160};
161
Michal Simekde29d542016-09-09 08:46:39 +0200[diff] [blame]162&dcc {
163 status = "okay";
164};
165
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]166&fpd_dma_chan1 {
167 status = "okay";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]168};
169
170&fpd_dma_chan2 {
171 status = "okay";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]172};
173
174&fpd_dma_chan3 {
175 status = "okay";
176};
177
178&fpd_dma_chan4 {
179 status = "okay";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]180};
181
182&fpd_dma_chan5 {
183 status = "okay";
184};
185
186&fpd_dma_chan6 {
187 status = "okay";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]188};
189
190&fpd_dma_chan7 {
191 status = "okay";
192};
193
194&fpd_dma_chan8 {
195 status = "okay";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]196};
197
198&gem3 {
199 status = "okay";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]200 phy-handle = <&phy0>;
201 phy-mode = "rgmii-id";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_gem3_default>;
Michal Simeka4224f22022-09-09 13:05:48 +0200[diff] [blame]204 mdio: mdio {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 phy0: ethernet-phy@21 {
208 #phy-cells = <1>;
209 compatible = "ethernet-phy-id2000.a231";
210 reg = <21>;
211 ti,rx-internal-delay = <0x8>;
212 ti,tx-internal-delay = <0xa>;
213 ti,fifo-depth = <0x1>;
214 ti,dp83867-rxctrl-strap-quirk;
Michal Simekf7a45b82022-09-09 13:05:49 +0200[diff] [blame]215 reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
Michal Simeka4224f22022-09-09 13:05:48 +0200[diff] [blame]216 };
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]217 };
218};
219
220&gpio {
221 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_gpio_default>;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]224};
225
226&gpu {
227 status = "okay";
228};
229
230&i2c0 {
231 status = "okay";
232 clock-frequency = <400000>;
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]233 pinctrl-names = "default", "gpio";
234 pinctrl-0 = <&pinctrl_i2c0_default>;
235 pinctrl-1 = <&pinctrl_i2c0_gpio>;
Manikanta Guntupallicc45c9c2023-07-10 14:37:28 +0200[diff] [blame]236 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
237 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]238
239 tca6416_u97: gpio@20 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]240 compatible = "ti,tca6416";
241 reg = <0x20>;
Michal Simeka545f5f2019-03-12 10:15:27 +0100[diff] [blame]242 gpio-controller; /* IRQ not connected */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]243 #gpio-cells = <2>;
Michal Simeka545f5f2019-03-12 10:15:27 +0100[diff] [blame]244 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
245 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
246 "", "", "", "", "", "", "", "", "";
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]247 gtr-sel0-hog {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]248 gpio-hog;
249 gpios = <0 0>;
Bharat Kumar Gogadae6464352017-01-30 12:06:02 +0530[diff] [blame]250 output-low; /* PCIE = 0, DP = 1 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]251 line-name = "sel0";
252 };
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]253 gtr-sel1-hog {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]254 gpio-hog;
255 gpios = <1 0>;
256 output-high; /* PCIE = 0, DP = 1 */
257 line-name = "sel1";
258 };
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]259 gtr-sel2-hog {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]260 gpio-hog;
261 gpios = <2 0>;
262 output-high; /* PCIE = 0, USB0 = 1 */
263 line-name = "sel2";
264 };
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]265 gtr-sel3-hog {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]266 gpio-hog;
267 gpios = <3 0>;
268 output-high; /* PCIE = 0, SATA = 1 */
269 line-name = "sel3";
270 };
271 };
272
Michal Simekd45b4402018-03-27 10:47:26 +0200[diff] [blame]273 tca6416_u61: gpio@21 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]274 compatible = "ti,tca6416";
275 reg = <0x21>;
Michal Simeka545f5f2019-03-12 10:15:27 +0100[diff] [blame]276 gpio-controller; /* IRQ not connected */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]277 #gpio-cells = <2>;
Michal Simeka545f5f2019-03-12 10:15:27 +0100[diff] [blame]278 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
279 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
280 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
281 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]282 };
283
Michal Simek2fde09e2018-03-27 10:38:08 +0200[diff] [blame]284 i2c-mux@75 { /* u60 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]285 compatible = "nxp,pca9544";
286 #address-cells = <1>;
287 #size-cells = <0>;
288 reg = <0x75>;
Michal Simekd45b4402018-03-27 10:47:26 +0200[diff] [blame]289 i2c@0 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]290 #address-cells = <1>;
291 #size-cells = <0>;
292 reg = <0>;
293 /* PS_PMBUS */
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]294 u76: ina226@40 { /* u76 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]295 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]296 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]297 label = "ina226-u76";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]298 reg = <0x40>;
299 shunt-resistor = <5000>;
300 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]301 u77: ina226@41 { /* u77 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]302 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]303 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]304 label = "ina226-u77";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]305 reg = <0x41>;
306 shunt-resistor = <5000>;
307 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]308 u78: ina226@42 { /* u78 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]309 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]310 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]311 label = "ina226-u78";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]312 reg = <0x42>;
313 shunt-resistor = <5000>;
314 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]315 u87: ina226@43 { /* u87 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]316 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]317 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]318 label = "ina226-u87";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]319 reg = <0x43>;
320 shunt-resistor = <5000>;
321 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]322 u85: ina226@44 { /* u85 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]323 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]324 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]325 label = "ina226-u85";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]326 reg = <0x44>;
327 shunt-resistor = <5000>;
328 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]329 u86: ina226@45 { /* u86 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]330 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]331 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]332 label = "ina226-u86";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]333 reg = <0x45>;
334 shunt-resistor = <5000>;
335 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]336 u93: ina226@46 { /* u93 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]337 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]338 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]339 label = "ina226-u93";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]340 reg = <0x46>;
341 shunt-resistor = <5000>;
342 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]343 u88: ina226@47 { /* u88 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]344 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]345 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]346 label = "ina226-u88";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]347 reg = <0x47>;
348 shunt-resistor = <5000>;
349 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]350 u15: ina226@4a { /* u15 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]351 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]352 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]353 label = "ina226-u15";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]354 reg = <0x4a>;
355 shunt-resistor = <5000>;
356 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]357 u92: ina226@4b { /* u92 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]358 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]359 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]360 label = "ina226-u92";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]361 reg = <0x4b>;
362 shunt-resistor = <5000>;
363 };
364 };
Michal Simekd45b4402018-03-27 10:47:26 +0200[diff] [blame]365 i2c@1 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]366 #address-cells = <1>;
367 #size-cells = <0>;
368 reg = <1>;
369 /* PL_PMBUS */
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]370 u79: ina226@40 { /* u79 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]371 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]372 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]373 label = "ina226-u79";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]374 reg = <0x40>;
375 shunt-resistor = <2000>;
376 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]377 u81: ina226@41 { /* u81 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]378 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]379 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]380 label = "ina226-u81";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]381 reg = <0x41>;
382 shunt-resistor = <5000>;
383 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]384 u80: ina226@42 { /* u80 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]385 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]386 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]387 label = "ina226-u80";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]388 reg = <0x42>;
389 shunt-resistor = <5000>;
390 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]391 u84: ina226@43 { /* u84 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]392 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]393 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]394 label = "ina226-u84";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]395 reg = <0x43>;
396 shunt-resistor = <5000>;
397 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]398 u16: ina226@44 { /* u16 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]399 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]400 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]401 label = "ina226-u16";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]402 reg = <0x44>;
403 shunt-resistor = <5000>;
404 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]405 u65: ina226@45 { /* u65 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]406 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]407 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]408 label = "ina226-u65";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]409 reg = <0x45>;
410 shunt-resistor = <5000>;
411 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]412 u74: ina226@46 { /* u74 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]413 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]414 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]415 label = "ina226-u74";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]416 reg = <0x46>;
417 shunt-resistor = <5000>;
418 };
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]419 u75: ina226@47 { /* u75 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]420 compatible = "ti,ina226";
Michal Simek41a41a42019-08-16 10:42:42 +0200[diff] [blame]421 #io-channel-cells = <1>;
Michal Simeka246bed2019-08-26 10:20:07 +0200[diff] [blame]422 label = "ina226-u75";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]423 reg = <0x47>;
424 shunt-resistor = <5000>;
425 };
426 };
Michal Simekd45b4402018-03-27 10:47:26 +0200[diff] [blame]427 i2c@2 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]428 #address-cells = <1>;
429 #size-cells = <0>;
430 reg = <2>;
431 /* MAXIM_PMBUS - 00 */
432 max15301@a { /* u46 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]433 compatible = "maxim,max15301";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]434 reg = <0xa>;
435 };
436 max15303@b { /* u4 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]437 compatible = "maxim,max15303";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]438 reg = <0xb>;
439 };
440 max15303@10 { /* u13 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]441 compatible = "maxim,max15303";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]442 reg = <0x10>;
443 };
444 max15301@13 { /* u47 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]445 compatible = "maxim,max15301";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]446 reg = <0x13>;
447 };
448 max15303@14 { /* u7 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]449 compatible = "maxim,max15303";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]450 reg = <0x14>;
451 };
452 max15303@15 { /* u6 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]453 compatible = "maxim,max15303";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]454 reg = <0x15>;
455 };
456 max15303@16 { /* u10 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]457 compatible = "maxim,max15303";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]458 reg = <0x16>;
459 };
460 max15303@17 { /* u9 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]461 compatible = "maxim,max15303";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]462 reg = <0x17>;
463 };
464 max15301@18 { /* u63 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]465 compatible = "maxim,max15301";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]466 reg = <0x18>;
467 };
468 max15303@1a { /* u49 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]469 compatible = "maxim,max15303";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]470 reg = <0x1a>;
471 };
472 max15303@1d { /* u18 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]473 compatible = "maxim,max15303";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]474 reg = <0x1d>;
475 };
476 max15303@20 { /* u8 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]477 compatible = "maxim,max15303";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]478 status = "disabled"; /* unreachable */
479 reg = <0x20>;
480 };
Michal Simek84dc3c02018-03-27 12:01:24 +0200[diff] [blame]481 max20751@72 { /* u95 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]482 compatible = "maxim,max20751";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]483 reg = <0x72>;
484 };
Michal Simek84dc3c02018-03-27 12:01:24 +0200[diff] [blame]485 max20751@73 { /* u96 */
Michal Simekcba5b322018-03-27 10:52:40 +0200[diff] [blame]486 compatible = "maxim,max20751";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]487 reg = <0x73>;
488 };
489 };
490 /* Bus 3 is not connected */
491 };
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]492};
493
494&i2c1 {
495 status = "okay";
496 clock-frequency = <400000>;
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]497 pinctrl-names = "default", "gpio";
498 pinctrl-0 = <&pinctrl_i2c1_default>;
499 pinctrl-1 = <&pinctrl_i2c1_gpio>;
Manikanta Guntupallicc45c9c2023-07-10 14:37:28 +0200[diff] [blame]500 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
501 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
Michal Simek6471f8e2017-11-02 11:51:59 +0100[diff] [blame]502
Michal Simek84dc3c02018-03-27 12:01:24 +0200[diff] [blame]503 /* PL i2c via PCA9306 - u45 */
Michal Simek2fde09e2018-03-27 10:38:08 +0200[diff] [blame]504 i2c-mux@74 { /* u34 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]505 compatible = "nxp,pca9548";
506 #address-cells = <1>;
507 #size-cells = <0>;
508 reg = <0x74>;
Michal Simekd45b4402018-03-27 10:47:26 +0200[diff] [blame]509 i2c@0 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]510 #address-cells = <1>;
511 #size-cells = <0>;
512 reg = <0>;
513 /*
514 * IIC_EEPROM 1kB memory which uses 256B blocks
515 * where every block has different address.
516 * 0 - 256B address 0x54
517 * 256B - 512B address 0x55
518 * 512B - 768B address 0x56
519 * 768B - 1024B address 0x57
520 */
Michal Simekc9ce08d2017-11-02 11:42:12 +0100[diff] [blame]521 eeprom: eeprom@54 { /* u23 */
Michal Simek28cf3ba2018-03-27 10:54:25 +0200[diff] [blame]522 compatible = "atmel,24c08";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]523 reg = <0x54>;
524 };
525 };
Michal Simekd45b4402018-03-27 10:47:26 +0200[diff] [blame]526 i2c@1 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]527 #address-cells = <1>;
528 #size-cells = <0>;
529 reg = <1>;
Michal Simek68ddc172018-03-27 10:39:53 +0200[diff] [blame]530 si5341: clock-generator@36 { /* SI5341 - u69 */
Michal Simek7b5a7a42018-03-27 12:48:30 +0200[diff] [blame]531 compatible = "silabs,si5341";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]532 reg = <0x36>;
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]533 #clock-cells = <2>;
534 #address-cells = <1>;
535 #size-cells = <0>;
536 clocks = <&ref48>;
537 clock-names = "xtal";
538 clock-output-names = "si5341";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]539
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]540 si5341_0: out@0 {
541 /* refclk0 for PS-GT, used for DP */
542 reg = <0>;
543 always-on;
544 };
545 si5341_2: out@2 {
546 /* refclk2 for PS-GT, used for USB3 */
547 reg = <2>;
548 always-on;
549 };
550 si5341_3: out@3 {
551 /* refclk3 for PS-GT, used for SATA */
552 reg = <3>;
553 always-on;
554 };
555 si5341_4: out@4 {
556 /* refclk4 for PS-GT, used for PCIE slot */
557 reg = <4>;
558 always-on;
559 };
560 si5341_5: out@5 {
561 /* refclk5 for PS-GT, used for PCIE */
562 reg = <5>;
563 always-on;
564 };
565 si5341_6: out@6 {
566 /* refclk6 PL CLK125 */
567 reg = <6>;
568 always-on;
569 };
570 si5341_7: out@7 {
571 /* refclk7 PL CLK74 */
572 reg = <7>;
573 always-on;
574 };
575 si5341_9: out@9 {
576 /* refclk9 used for PS_REF_CLK 33.3 MHz */
577 reg = <9>;
578 always-on;
579 };
580 };
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]581 };
Michal Simekd45b4402018-03-27 10:47:26 +0200[diff] [blame]582 i2c@2 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]583 #address-cells = <1>;
584 #size-cells = <0>;
585 reg = <2>;
Michal Simek68ddc172018-03-27 10:39:53 +0200[diff] [blame]586 si570_1: clock-generator@5d { /* USER SI570 - u42 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]587 #clock-cells = <0>;
588 compatible = "silabs,si570";
589 reg = <0x5d>;
590 temperature-stability = <50>;
591 factory-fout = <300000000>;
592 clock-frequency = <300000000>;
Michal Simek3cf07bf2018-07-18 12:10:02 +0200[diff] [blame]593 clock-output-names = "si570_user";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]594 };
595 };
Michal Simekd45b4402018-03-27 10:47:26 +0200[diff] [blame]596 i2c@3 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]597 #address-cells = <1>;
598 #size-cells = <0>;
599 reg = <3>;
Michal Simek68ddc172018-03-27 10:39:53 +0200[diff] [blame]600 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]601 #clock-cells = <0>;
602 compatible = "silabs,si570";
603 reg = <0x5d>;
604 temperature-stability = <50>; /* copy from zc702 */
605 factory-fout = <156250000>;
Michal Simek9c7b8362023-08-25 09:11:29 +0200[diff] [blame]606 clock-frequency = <156250000>;
Michal Simek3cf07bf2018-07-18 12:10:02 +0200[diff] [blame]607 clock-output-names = "si570_mgt";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]608 };
609 };
Michal Simekd45b4402018-03-27 10:47:26 +0200[diff] [blame]610 i2c@4 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]611 #address-cells = <1>;
612 #size-cells = <0>;
613 reg = <4>;
Michal Simek345508b2022-05-11 11:52:54 +0200[diff] [blame]614 si5328: clock-generator@69 {/* SI5328 - u20 */
615 compatible = "silabs,si5328";
616 reg = <0x69>;
617 /*
618 * Chip has interrupt present connected to PL
619 * interrupt-parent = <&>;
620 * interrupts = <>;
621 */
622 #address-cells = <1>;
623 #size-cells = <0>;
624 #clock-cells = <1>;
625 clocks = <&refhdmi>;
626 clock-names = "xtal";
627 clock-output-names = "si5328";
628
629 si5328_clk: clk0@0 {
630 reg = <0>;
631 clock-frequency = <27000000>;
632 };
633 };
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]634 };
635 /* 5 - 7 unconnected */
636 };
637
Michal Simek2fde09e2018-03-27 10:38:08 +0200[diff] [blame]638 i2c-mux@75 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]639 compatible = "nxp,pca9548"; /* u135 */
640 #address-cells = <1>;
641 #size-cells = <0>;
642 reg = <0x75>;
643
644 i2c@0 {
645 #address-cells = <1>;
646 #size-cells = <0>;
647 reg = <0>;
648 /* HPC0_IIC */
649 };
650 i2c@1 {
651 #address-cells = <1>;
652 #size-cells = <0>;
653 reg = <1>;
654 /* HPC1_IIC */
655 };
656 i2c@2 {
657 #address-cells = <1>;
658 #size-cells = <0>;
659 reg = <2>;
660 /* SYSMON */
661 };
Michal Simekd45b4402018-03-27 10:47:26 +0200[diff] [blame]662 i2c@3 {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]663 #address-cells = <1>;
664 #size-cells = <0>;
665 reg = <3>;
666 /* DDR4 SODIMM */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]667 };
668 i2c@4 {
669 #address-cells = <1>;
670 #size-cells = <0>;
671 reg = <4>;
672 /* SEP 3 */
673 };
674 i2c@5 {
675 #address-cells = <1>;
676 #size-cells = <0>;
677 reg = <5>;
678 /* SEP 2 */
679 };
680 i2c@6 {
681 #address-cells = <1>;
682 #size-cells = <0>;
683 reg = <6>;
684 /* SEP 1 */
685 };
686 i2c@7 {
687 #address-cells = <1>;
688 #size-cells = <0>;
689 reg = <7>;
690 /* SEP 0 */
691 };
692 };
693};
694
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]695&pinctrl0 {
696 status = "okay";
697 pinctrl_i2c0_default: i2c0-default {
698 mux {
699 groups = "i2c0_3_grp";
700 function = "i2c0";
701 };
702
703 conf {
704 groups = "i2c0_3_grp";
705 bias-pull-up;
706 slew-rate = <SLEW_RATE_SLOW>;
707 power-source = <IO_STANDARD_LVCMOS18>;
708 };
709 };
710
Michal Simekcf3cd802023-12-19 17:16:50 +0100[diff] [blame^]711 pinctrl_i2c0_gpio: i2c0-gpio-grp {
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]712 mux {
713 groups = "gpio0_14_grp", "gpio0_15_grp";
714 function = "gpio0";
715 };
716
717 conf {
718 groups = "gpio0_14_grp", "gpio0_15_grp";
719 slew-rate = <SLEW_RATE_SLOW>;
720 power-source = <IO_STANDARD_LVCMOS18>;
721 };
722 };
723
724 pinctrl_i2c1_default: i2c1-default {
725 mux {
726 groups = "i2c1_4_grp";
727 function = "i2c1";
728 };
729
730 conf {
731 groups = "i2c1_4_grp";
732 bias-pull-up;
733 slew-rate = <SLEW_RATE_SLOW>;
734 power-source = <IO_STANDARD_LVCMOS18>;
735 };
736 };
737
Michal Simekcf3cd802023-12-19 17:16:50 +0100[diff] [blame^]738 pinctrl_i2c1_gpio: i2c1-gpio-grp {
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]739 mux {
740 groups = "gpio0_16_grp", "gpio0_17_grp";
741 function = "gpio0";
742 };
743
744 conf {
745 groups = "gpio0_16_grp", "gpio0_17_grp";
746 slew-rate = <SLEW_RATE_SLOW>;
747 power-source = <IO_STANDARD_LVCMOS18>;
748 };
749 };
750
751 pinctrl_uart0_default: uart0-default {
752 mux {
753 groups = "uart0_4_grp";
754 function = "uart0";
755 };
756
757 conf {
758 groups = "uart0_4_grp";
759 slew-rate = <SLEW_RATE_SLOW>;
760 power-source = <IO_STANDARD_LVCMOS18>;
761 };
762
763 conf-rx {
764 pins = "MIO18";
765 bias-high-impedance;
766 };
767
768 conf-tx {
769 pins = "MIO19";
770 bias-disable;
771 };
772 };
773
774 pinctrl_uart1_default: uart1-default {
775 mux {
776 groups = "uart1_5_grp";
777 function = "uart1";
778 };
779
780 conf {
781 groups = "uart1_5_grp";
782 slew-rate = <SLEW_RATE_SLOW>;
783 power-source = <IO_STANDARD_LVCMOS18>;
784 };
785
786 conf-rx {
787 pins = "MIO21";
788 bias-high-impedance;
789 };
790
791 conf-tx {
792 pins = "MIO20";
793 bias-disable;
794 };
795 };
796
797 pinctrl_usb0_default: usb0-default {
798 mux {
799 groups = "usb0_0_grp";
800 function = "usb0";
801 };
802
803 conf {
804 groups = "usb0_0_grp";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]805 power-source = <IO_STANDARD_LVCMOS18>;
806 };
807
808 conf-rx {
809 pins = "MIO52", "MIO53", "MIO55";
810 bias-high-impedance;
Ashok Reddy Soma4d0ecf62022-06-15 12:16:13 +0200[diff] [blame]811 drive-strength = <12>;
812 slew-rate = <SLEW_RATE_FAST>;
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]813 };
814
815 conf-tx {
816 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
817 "MIO60", "MIO61", "MIO62", "MIO63";
818 bias-disable;
Ashok Reddy Soma4d0ecf62022-06-15 12:16:13 +0200[diff] [blame]819 drive-strength = <4>;
820 slew-rate = <SLEW_RATE_SLOW>;
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]821 };
822 };
823
824 pinctrl_gem3_default: gem3-default {
825 mux {
826 function = "ethernet3";
827 groups = "ethernet3_0_grp";
828 };
829
830 conf {
831 groups = "ethernet3_0_grp";
832 slew-rate = <SLEW_RATE_SLOW>;
833 power-source = <IO_STANDARD_LVCMOS18>;
834 };
835
836 conf-rx {
837 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
838 "MIO75";
839 bias-high-impedance;
840 low-power-disable;
841 };
842
843 conf-tx {
844 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
845 "MIO69";
846 bias-disable;
847 low-power-enable;
848 };
849
850 mux-mdio {
851 function = "mdio3";
852 groups = "mdio3_0_grp";
853 };
854
855 conf-mdio {
856 groups = "mdio3_0_grp";
857 slew-rate = <SLEW_RATE_SLOW>;
858 power-source = <IO_STANDARD_LVCMOS18>;
859 bias-disable;
860 };
861 };
862
863 pinctrl_can1_default: can1-default {
864 mux {
865 function = "can1";
866 groups = "can1_6_grp";
867 };
868
869 conf {
870 groups = "can1_6_grp";
871 slew-rate = <SLEW_RATE_SLOW>;
872 power-source = <IO_STANDARD_LVCMOS18>;
873 };
874
875 conf-rx {
876 pins = "MIO25";
877 bias-high-impedance;
878 };
879
880 conf-tx {
881 pins = "MIO24";
882 bias-disable;
883 };
884 };
885
886 pinctrl_sdhci1_default: sdhci1-default {
887 mux {
888 groups = "sdio1_0_grp";
889 function = "sdio1";
890 };
891
892 conf {
893 groups = "sdio1_0_grp";
894 slew-rate = <SLEW_RATE_SLOW>;
895 power-source = <IO_STANDARD_LVCMOS18>;
896 bias-disable;
897 };
898
899 mux-cd {
900 groups = "sdio1_cd_0_grp";
901 function = "sdio1_cd";
902 };
903
904 conf-cd {
905 groups = "sdio1_cd_0_grp";
906 bias-high-impedance;
907 bias-pull-up;
908 slew-rate = <SLEW_RATE_SLOW>;
909 power-source = <IO_STANDARD_LVCMOS18>;
910 };
911
912 mux-wp {
913 groups = "sdio1_wp_0_grp";
914 function = "sdio1_wp";
915 };
916
917 conf-wp {
918 groups = "sdio1_wp_0_grp";
919 bias-high-impedance;
920 bias-pull-up;
921 slew-rate = <SLEW_RATE_SLOW>;
922 power-source = <IO_STANDARD_LVCMOS18>;
923 };
924 };
925
926 pinctrl_gpio_default: gpio-default {
927 mux-sw {
928 function = "gpio0";
929 groups = "gpio0_22_grp", "gpio0_23_grp";
930 };
931
932 conf-sw {
933 groups = "gpio0_22_grp", "gpio0_23_grp";
934 slew-rate = <SLEW_RATE_SLOW>;
935 power-source = <IO_STANDARD_LVCMOS18>;
936 };
937
938 mux-msp {
939 function = "gpio0";
940 groups = "gpio0_13_grp", "gpio0_38_grp";
941 };
942
943 conf-msp {
944 groups = "gpio0_13_grp", "gpio0_38_grp";
945 slew-rate = <SLEW_RATE_SLOW>;
946 power-source = <IO_STANDARD_LVCMOS18>;
947 };
948
949 conf-pull-up {
950 pins = "MIO22", "MIO23";
951 bias-pull-up;
952 };
953
954 conf-pull-none {
955 pins = "MIO13", "MIO38";
956 bias-disable;
957 };
958 };
959};
960
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]961&pcie {
Bharat Kumar Gogadae6464352017-01-30 12:06:02 +0530[diff] [blame]962 status = "okay";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]963};
964
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]965&psgtr {
966 status = "okay";
967 /* pcie, sata, usb3, dp */
968 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
969 clock-names = "ref0", "ref1", "ref2", "ref3";
970};
971
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]972&qspi {
973 status = "okay";
Michal Simek27c83202023-09-22 12:35:43 +0200[diff] [blame]974 num-cs = <2>;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]975 flash@0 {
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]976 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]977 #address-cells = <1>;
978 #size-cells = <1>;
Michal Simek27c83202023-09-22 12:35:43 +0200[diff] [blame]979 reg = <0>, <1>;
980 parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
Amit Kumar Mahapatraa02408b2022-05-10 16:33:01 +0200[diff] [blame]981 spi-tx-bus-width = <4>;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]982 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
983 spi-max-frequency = <108000000>; /* Based on DC1 spec */
Michal Simek70fafdf2020-02-14 14:19:56 +0100[diff] [blame]984 partition@0 { /* for testing purpose */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]985 label = "qspi-fsbl-uboot";
986 reg = <0x0 0x100000>;
987 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100[diff] [blame]988 partition@100000 { /* for testing purpose */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]989 label = "qspi-linux";
990 reg = <0x100000 0x500000>;
991 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100[diff] [blame]992 partition@600000 { /* for testing purpose */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]993 label = "qspi-device-tree";
994 reg = <0x600000 0x20000>;
995 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100[diff] [blame]996 partition@620000 { /* for testing purpose */
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]997 label = "qspi-rootfs";
998 reg = <0x620000 0x5E0000>;
999 };
1000 };
1001};
1002
1003&rtc {
1004 status = "okay";
1005};
1006
1007&sata {
1008 status = "okay";
1009 /* SATA OOB timing settings */
1010 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
1011 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
1012 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
1013 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
1014 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
1015 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
1016 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
1017 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
Michal Simekd5ba4f22017-12-01 15:50:31 +0100[diff] [blame]1018 phy-names = "sata-phy";
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]1019 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]1020};
1021
1022/* SD1 with level shifter */
1023&sdhci1 {
1024 status = "okay";
Manish Naranie2ba0932020-02-13 23:37:30 -0700[diff] [blame]1025 /*
1026 * 1.0 revision has level shifter and this property should be
1027 * removed for supporting UHS mode
1028 */
1029 no-1-8-v;
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]1030 pinctrl-names = "default";
1031 pinctrl-0 = <&pinctrl_sdhci1_default>;
Michal Simek3b662642020-07-22 17:42:43 +0200[diff] [blame]1032 xlnx,mio-bank = <1>;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]1033};
1034
1035&uart0 {
1036 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]1037 pinctrl-names = "default";
1038 pinctrl-0 = <&pinctrl_uart0_default>;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]1039};
1040
1041&uart1 {
1042 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]1043 pinctrl-names = "default";
1044 pinctrl-0 = <&pinctrl_uart1_default>;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]1045};
1046
1047/* ULPI SMSC USB3320 */
1048&usb0 {
1049 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]1050 pinctrl-names = "default";
1051 pinctrl-0 = <&pinctrl_usb0_default>;
Manish Naranif3c63382021-07-14 06:17:19 -0600[diff] [blame]1052 phy-names = "usb3-phy";
1053 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]1054};
1055
1056&dwc3_0 {
1057 status = "okay";
1058 dr_mode = "host";
Michal Simekd5ba4f22017-12-01 15:50:31 +0100[diff] [blame]1059 snps,usb3_lpm_capable;
Michal Simekd5ba4f22017-12-01 15:50:31 +0100[diff] [blame]1060 maximum-speed = "super-speed";
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]1061};
1062
Shubhrajyoti Dattae036cd62017-04-06 12:28:14 +0530[diff] [blame]1063&watchdog0 {
1064 status = "okay";
1065};
1066
Michal Simek1bb4be32017-11-02 12:04:43 +0100[diff] [blame]1067&xilinx_ams {
1068 status = "okay";
1069};
1070
1071&ams_ps {
1072 status = "okay";
1073};
1074
1075&ams_pl {
1076 status = "okay";
1077};
1078
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]1079&zynqmp_dpdma {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]1080 status = "okay";
1081};
1082
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]1083&zynqmp_dpsub {
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]1084 status = "okay";
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]1085 phy-names = "dp-phy0";
1086 phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
Michal Simek5fc61c82016-04-07 15:58:23 +0200[diff] [blame]1087};