blob: 66628933b65398ffa6c60f614e7c269449451828 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jimmy Zhanga308d462012-04-10 05:17:06 +00002/*
3 * Copyright (c) 2011 The Chromium OS Authors.
Jimmy Zhanga308d462012-04-10 05:17:06 +00004 */
5
6#include <common.h>
Jeroen Hofstee93dfae72014-10-08 22:57:46 +02007#include "emc.h"
Jimmy Zhanga308d462012-04-10 05:17:06 +00008#include <asm/io.h>
Jimmy Zhanga308d462012-04-10 05:17:06 +00009#include <asm/arch/clock.h>
10#include <asm/arch/emc.h>
Tom Warrenab371962012-09-19 15:50:56 -070011#include <asm/arch/tegra.h>
12#include <asm/arch-tegra/ap.h>
13#include <asm/arch-tegra/clk_rst.h>
Thierry Redingcf390082019-04-15 11:32:17 +020014#include <asm/arch-tegra/pmu.h>
Tom Warrenab371962012-09-19 15:50:56 -070015#include <asm/arch-tegra/sys_proto.h>
Jimmy Zhanga308d462012-04-10 05:17:06 +000016
17DECLARE_GLOBAL_DATA_PTR;
18
19/* These rates are hard-coded for now, until fdt provides them */
20#define EMC_SDRAM_RATE_T20 (333000 * 2 * 1000)
21#define EMC_SDRAM_RATE_T25 (380000 * 2 * 1000)
22
23int board_emc_init(void)
24{
25 unsigned rate;
26
Tom Warren8b817112013-04-10 10:32:32 -070027 switch (tegra_get_chip_sku()) {
Jimmy Zhanga308d462012-04-10 05:17:06 +000028 default:
29 case TEGRA_SOC_T20:
30 rate = EMC_SDRAM_RATE_T20;
31 break;
32 case TEGRA_SOC_T25:
33 rate = EMC_SDRAM_RATE_T25;
34 break;
35 }
36 return tegra_set_emc(gd->fdt_blob, rate);
37}