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git01.mediatek.com / filogic / uboot / cf1f4bb343ca1d19e09c89432367274786dfa873 / . / arch / arm / dts / stm32mp15xx-dhcor-testbench-u-boot.dtsi
blob: 31995c058eb401f9634608c64fda0a7765ef1760 [file] [log] [blame]
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "stm32mp15xx-dhcor-u-boot.dtsi"
7
8/ {
9 aliases {
10 mmc0 = &sdmmc1;
11 mmc1 = &sdmmc2;
12 usb0 = &usbotg_hs;
13 };
14
15 config {
16 dh,board-coding-gpios = <&gpiog 13 0>, <&gpiod 9 0>;
17 };
18};
19
20&ethernet0 {
21 phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
22
23 mdio0 {
24 ethernet-phy@7 {
25 reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
26 reset-assert-us = <11000>;
27 reset-deassert-us = <1000>;
28 };
29 };
30};
31
32&sdmmc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]34 st,use-ckin;
35 st,cmd-gpios = <&gpiod 2 0>;
36 st,ck-gpios = <&gpioc 12 0>;
37 st,ckin-gpios = <&gpioe 4 0>;
38};
39
40&sdmmc1_b4_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]42 pins1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]44 };
45 pins2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]47 };
48};
49
50&sdmmc1_dir_pins_b {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]52 pins1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]54 };
55 pins2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]57 };
58};
59
60&sdmmc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]62};
63
64&sdmmc2_b4_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]66 pins1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]68 };
69 pins2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]71 };
72};
73
74&sdmmc2_d47_pins_c {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]76 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]78 };
79};
80
81&uart4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-all;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]83};
84
85&uart4_pins_b {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-all;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]87 pins1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-all;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]89 };
90 pins2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-all;
Marek Vasut52784942022-09-26 18:50:00 +0200[diff] [blame]92 /delete-property/ bias-disable;
93 bias-pull-up;
94 };
95};
96
97&usbotg_hs {
98 u-boot,force-b-session-valid;
99 hnp-srp-disable;
100};