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git01.mediatek.com / filogic / uboot / cf0a4bad130d6d191e67563af465ddc108398d26 / . / configs / tinker-rk3288_defconfig
blob: cec39384b3c614de69173cc1f470b23d612785ea [file] [log] [blame]
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ROCKCHIP_RK3288=y
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]5CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
Eddie Cai1e1a79f2017-01-18 11:03:54 +0800[diff] [blame]6CONFIG_TARGET_TINKER_RK3288=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]7CONFIG_SPL_STACK_R_ADDR=0x80000
Eddie Cai1e1a79f2017-01-18 11:03:54 +0800[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
Simon Glass4458d3b2016-10-17 20:12:35 -0600[diff] [blame]9CONFIG_SILENT_CONSOLE=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]10CONFIG_CONSOLE_MUX=y
11# CONFIG_DISPLAY_CPUINFO is not set
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]12CONFIG_SPL_STACK_R=y
13CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]14# CONFIG_CMD_IMLS is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]15CONFIG_CMD_GPT=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]16CONFIG_CMD_MMC=y
17CONFIG_CMD_SF=y
18CONFIG_CMD_SPI=y
19CONFIG_CMD_I2C=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]20CONFIG_CMD_USB=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]21CONFIG_CMD_GPIO=y
22# CONFIG_CMD_SETEXPR is not set
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]23CONFIG_CMD_CACHE=y
24CONFIG_CMD_TIME=y
25CONFIG_CMD_PMIC=y
26CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]27# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay21d3bce2017-01-27 11:00:38 +0100[diff] [blame]28# CONFIG_SPL_ISO_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]29# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]30CONFIG_SPL_PARTITION_UUIDS=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]31CONFIG_SPL_OF_CONTROL=y
32CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
33CONFIG_REGMAP=y
34CONFIG_SPL_REGMAP=y
35CONFIG_SYSCON=y
36CONFIG_SPL_SYSCON=y
37# CONFIG_SPL_SIMPLE_BUS is not set
38CONFIG_CLK=y
39CONFIG_SPL_CLK=y
40CONFIG_ROCKCHIP_GPIO=y
41CONFIG_SYS_I2C_ROCKCHIP=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]42CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]43CONFIG_MMC_DW_ROCKCHIP=y
Jacob Chen5c3166d2017-02-23 14:20:17 +0800[diff] [blame]44CONFIG_DM_ETH=y
45CONFIG_NETDEVICES=y
46CONFIG_ETH_DESIGNWARE=y
47CONFIG_GMAC_ROCKCHIP=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]48CONFIG_PINCTRL=y
49CONFIG_SPL_PINCTRL=y
50# CONFIG_SPL_PINCTRL_FULL is not set
51CONFIG_ROCKCHIP_RK3288_PINCTRL=y
52CONFIG_DM_PMIC=y
53CONFIG_PMIC_RK808=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]54CONFIG_DM_REGULATOR_FIXED=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]55CONFIG_REGULATOR_RK808=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]56CONFIG_PWM_ROCKCHIP=y
57CONFIG_RAM=y
58CONFIG_SPL_RAM=y
59CONFIG_DEBUG_UART=y
60CONFIG_DEBUG_UART_BASE=0xff690000
61CONFIG_DEBUG_UART_CLOCK=24000000
62CONFIG_DEBUG_UART_SHIFT=2
63CONFIG_SYS_NS16550=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]64CONFIG_SYSRESET=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]65CONFIG_USB=y
66CONFIG_USB_STORAGE=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]67CONFIG_USE_TINY_PRINTF=y
68CONFIG_CMD_DHRYSTONE=y
69CONFIG_ERRNO_STR=y