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git01.mediatek.com / filogic / uboot / cefdc034bbf172d12e1278e478ee28f2f0241d0c / . / arch / arm / dts / sama5d4.dtsi
blob: 5e2c9a1db2ff93d7fda58849169e3d4d405ada60 [file] [log] [blame]
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]1/*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/clock/at91.h>
48#include <dt-bindings/dma/at91.h>
49#include <dt-bindings/pinctrl/at91.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "Atmel SAMA5D4 family SoC";
55 compatible = "atmel,sama5d4";
56 interrupt-parent = <&aic>;
57
58 aliases {
59 serial0 = &usart3;
60 serial1 = &usart4;
61 serial2 = &usart2;
62 serial3 = &usart0;
63 serial4 = &usart1;
64 serial5 = &uart0;
65 serial6 = &uart1;
66 gpio0 = &pioA;
67 gpio1 = &pioB;
68 gpio2 = &pioC;
69 gpio3 = &pioD;
70 gpio4 = &pioE;
71 pwm0 = &pwm0;
72 ssc0 = &ssc0;
73 ssc1 = &ssc1;
74 tcb0 = &tcb0;
75 tcb1 = &tcb1;
76 i2c0 = &i2c0;
77 i2c1 = &i2c1;
78 i2c2 = &i2c2;
79 };
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu@0 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a5";
87 reg = <0>;
88 next-level-cache = <&L2>;
89 };
90 };
91
92 memory {
93 reg = <0x20000000 0x20000000>;
94 };
95
96 clocks {
97 slow_xtal: slow_xtal {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <0>;
101 };
102
103 main_xtal: main_xtal {
104 compatible = "fixed-clock";
105 #clock-cells = <0>;
106 clock-frequency = <0>;
107 };
108
109 adc_op_clk: adc_op_clk{
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <1000000>;
113 };
114 };
115
116 ns_sram: sram@00210000 {
117 compatible = "mmio-sram";
118 reg = <0x00210000 0x10000>;
119 };
120
121 ahb {
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]127
128 usb0: gadget@00400000 {
129 #address-cells = <1>;
130 #size-cells = <0>;
131 compatible = "atmel,sama5d3-udc";
132 reg = <0x00400000 0x100000
133 0xfc02c000 0x4000>;
134 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
135 clocks = <&udphs_clk>, <&utmi>;
136 clock-names = "pclk", "hclk";
137 status = "disabled";
138
139 ep0: endpoint@0 {
140 reg = <0>;
141 atmel,fifo-size = <64>;
142 atmel,nb-banks = <1>;
143 };
144
145 ep1: endpoint@1 {
146 reg = <1>;
147 atmel,fifo-size = <1024>;
148 atmel,nb-banks = <3>;
149 atmel,can-dma;
150 atmel,can-isoc;
151 };
152
153 ep2: endpoint@2 {
154 reg = <2>;
155 atmel,fifo-size = <1024>;
156 atmel,nb-banks = <3>;
157 atmel,can-dma;
158 atmel,can-isoc;
159 };
160
161 ep3: endpoint@3 {
162 reg = <3>;
163 atmel,fifo-size = <1024>;
164 atmel,nb-banks = <2>;
165 atmel,can-dma;
166 atmel,can-isoc;
167 };
168
169 ep4: endpoint@4 {
170 reg = <4>;
171 atmel,fifo-size = <1024>;
172 atmel,nb-banks = <2>;
173 atmel,can-dma;
174 atmel,can-isoc;
175 };
176
177 ep5: endpoint@5 {
178 reg = <5>;
179 atmel,fifo-size = <1024>;
180 atmel,nb-banks = <2>;
181 atmel,can-dma;
182 atmel,can-isoc;
183 };
184
185 ep6: endpoint@6 {
186 reg = <6>;
187 atmel,fifo-size = <1024>;
188 atmel,nb-banks = <2>;
189 atmel,can-dma;
190 atmel,can-isoc;
191 };
192
193 ep7: endpoint@7 {
194 reg = <7>;
195 atmel,fifo-size = <1024>;
196 atmel,nb-banks = <2>;
197 atmel,can-dma;
198 atmel,can-isoc;
199 };
200
201 ep8: endpoint@8 {
202 reg = <8>;
203 atmel,fifo-size = <1024>;
204 atmel,nb-banks = <2>;
205 atmel,can-isoc;
206 };
207
208 ep9: endpoint@9 {
209 reg = <9>;
210 atmel,fifo-size = <1024>;
211 atmel,nb-banks = <2>;
212 atmel,can-isoc;
213 };
214
Eugen Hristev0e286592020-06-05 09:51:30 +0300[diff] [blame]215 ep10: endpoint@a {
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]216 reg = <10>;
217 atmel,fifo-size = <1024>;
218 atmel,nb-banks = <2>;
219 atmel,can-isoc;
220 };
221
Eugen Hristev0e286592020-06-05 09:51:30 +0300[diff] [blame]222 ep11: endpoint@b {
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]223 reg = <11>;
224 atmel,fifo-size = <1024>;
225 atmel,nb-banks = <2>;
226 atmel,can-isoc;
227 };
228
Eugen Hristev0e286592020-06-05 09:51:30 +0300[diff] [blame]229 ep12: endpoint@c {
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]230 reg = <12>;
231 atmel,fifo-size = <1024>;
232 atmel,nb-banks = <2>;
233 atmel,can-isoc;
234 };
235
Eugen Hristev0e286592020-06-05 09:51:30 +0300[diff] [blame]236 ep13: endpoint@d {
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]237 reg = <13>;
238 atmel,fifo-size = <1024>;
239 atmel,nb-banks = <2>;
240 atmel,can-isoc;
241 };
242
Eugen Hristev0e286592020-06-05 09:51:30 +0300[diff] [blame]243 ep14: endpoint@e {
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]244 reg = <14>;
245 atmel,fifo-size = <1024>;
246 atmel,nb-banks = <2>;
247 atmel,can-isoc;
248 };
249
Eugen Hristev0e286592020-06-05 09:51:30 +0300[diff] [blame]250 ep15: endpoint@f {
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]251 reg = <15>;
252 atmel,fifo-size = <1024>;
253 atmel,nb-banks = <2>;
254 atmel,can-isoc;
255 };
256 };
257
258 usb1: ohci@00500000 {
259 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
260 reg = <0x00500000 0x100000>;
261 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
262 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
263 clock-names = "ohci_clk", "hclk", "uhpck";
264 status = "disabled";
265 };
266
267 usb2: ehci@00600000 {
268 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
269 reg = <0x00600000 0x100000>;
270 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
271 clocks = <&utmi>, <&uhphs_clk>;
272 clock-names = "usb_clk", "ehci_clk";
273 status = "disabled";
274 };
275
276 L2: cache-controller@00a00000 {
277 compatible = "arm,pl310-cache";
278 reg = <0x00a00000 0x1000>;
279 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
280 cache-unified;
281 cache-level = <2>;
282 };
283
284 nand0: nand@80000000 {
285 compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
286 #address-cells = <1>;
287 #size-cells = <1>;
288 ranges;
289 reg = < 0x80000000 0x08000000 /* EBI CS3 */
290 0xfc05c070 0x00000490 /* SMC PMECC regs */
291 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
292 >;
293 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
294 atmel,nand-addr-offset = <21>;
295 atmel,nand-cmd-offset = <22>;
296 atmel,nand-has-dma;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_nand>;
299 status = "disabled";
300
301 nfc@90000000 {
302 compatible = "atmel,sama5d3-nfc";
303 #address-cells = <1>;
304 #size-cells = <1>;
305 reg = <
306 0x90000000 0x08000000 /* NFC Command Registers */
307 0xfc05c000 0x00000070 /* NFC HSMC regs */
308 0x00100000 0x00100000 /* NFC SRAM banks */
309 >;
310 clocks = <&hsmc_clk>;
311 atmel,write-by-sram;
312 };
313 };
314
315 apb {
316 compatible = "simple-bus";
317 #address-cells = <1>;
318 #size-cells = <1>;
319 ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]320 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]321
322 hlcdc: hlcdc@f0000000 {
Wenyou Yang426691e2017-09-18 15:26:00 +0800[diff] [blame]323 compatible = "atmel,at91sam9x5-hlcdc";
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]324 reg = <0xf0000000 0x4000>;
325 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
326 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
327 clock-names = "periph_clk","sys_clk", "slow_clk";
328 status = "disabled";
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]329 };
330
331 dma1: dma-controller@f0004000 {
332 compatible = "atmel,sama5d4-dma";
333 reg = <0xf0004000 0x200>;
334 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
335 #dma-cells = <1>;
336 clocks = <&dma1_clk>;
337 clock-names = "dma_clk";
338 };
339
340 isi: isi@f0008000 {
341 compatible = "atmel,at91sam9g45-isi";
342 reg = <0xf0008000 0x4000>;
343 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_isi_data_0_7>;
346 clocks = <&isi_clk>;
347 clock-names = "isi_clk";
348 status = "disabled";
349 port {
350 #address-cells = <1>;
351 #size-cells = <0>;
352 };
353 };
354
355 ramc0: ramc@f0010000 {
356 compatible = "atmel,sama5d3-ddramc";
357 reg = <0xf0010000 0x200>;
358 clocks = <&ddrck>, <&mpddr_clk>;
359 clock-names = "ddrck", "mpddr";
360 };
361
362 dma0: dma-controller@f0014000 {
363 compatible = "atmel,sama5d4-dma";
364 reg = <0xf0014000 0x200>;
365 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
366 #dma-cells = <1>;
367 clocks = <&dma0_clk>;
368 clock-names = "dma_clk";
369 };
370
371 pmc: pmc@f0018000 {
372 compatible = "atmel,sama5d3-pmc", "syscon";
373 reg = <0xf0018000 0x120>;
374 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
375 interrupt-controller;
376 #address-cells = <1>;
377 #size-cells = <0>;
378 #interrupt-cells = <1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]379 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]380
381 main_rc_osc: main_rc_osc {
382 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
383 #clock-cells = <0>;
384 interrupt-parent = <&pmc>;
385 interrupts = <AT91_PMC_MOSCRCS>;
386 clock-frequency = <12000000>;
387 clock-accuracy = <100000000>;
388 };
389
390 main_osc: main_osc {
391 compatible = "atmel,at91rm9200-clk-main-osc";
392 #clock-cells = <0>;
393 interrupt-parent = <&pmc>;
394 interrupts = <AT91_PMC_MOSCS>;
395 clocks = <&main_xtal>;
396 };
397
398 main: mainck {
399 compatible = "atmel,at91sam9x5-clk-main";
400 #clock-cells = <0>;
401 interrupt-parent = <&pmc>;
402 interrupts = <AT91_PMC_MOSCSELS>;
403 clocks = <&main_rc_osc &main_osc>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]404 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]405 };
406
407 plla: pllack@0 {
408 compatible = "atmel,sama5d3-clk-pll";
409 #clock-cells = <0>;
410 interrupt-parent = <&pmc>;
411 interrupts = <AT91_PMC_LOCKA>;
412 clocks = <&main>;
413 reg = <0>;
414 atmel,clk-input-range = <12000000 12000000>;
415 #atmel,pll-clk-output-range-cells = <4>;
416 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
417 };
418
419 plladiv: plladivck {
420 compatible = "atmel,at91sam9x5-clk-plldiv";
421 #clock-cells = <0>;
422 clocks = <&plla>;
423 };
424
425 utmi: utmick {
426 compatible = "atmel,at91sam9x5-clk-utmi";
427 #clock-cells = <0>;
428 interrupt-parent = <&pmc>;
429 interrupts = <AT91_PMC_LOCKU>;
430 clocks = <&main>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]431 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]432 };
433
434 mck: masterck {
435 compatible = "atmel,at91sam9x5-clk-master";
436 #clock-cells = <0>;
437 interrupt-parent = <&pmc>;
438 interrupts = <AT91_PMC_MCKRDY>;
439 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
440 atmel,clk-output-range = <125000000 200000000>;
441 atmel,clk-divisors = <1 2 4 3>;
442 };
443
444 h32ck: h32mxck {
445 #clock-cells = <0>;
446 compatible = "atmel,sama5d4-clk-h32mx";
447 clocks = <&mck>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]448 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]449 };
450
451 usb: usbck {
452 compatible = "atmel,at91sam9x5-clk-usb";
453 #clock-cells = <0>;
454 clocks = <&plladiv>, <&utmi>;
455 };
456
457 prog: progck {
458 compatible = "atmel,at91sam9x5-clk-programmable";
459 #address-cells = <1>;
460 #size-cells = <0>;
461 interrupt-parent = <&pmc>;
462 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
463
464 prog0: prog@0 {
465 #clock-cells = <0>;
466 reg = <0>;
467 interrupts = <AT91_PMC_PCKRDY(0)>;
468 };
469
470 prog1: prog@1 {
471 #clock-cells = <0>;
472 reg = <1>;
473 interrupts = <AT91_PMC_PCKRDY(1)>;
474 };
475
476 prog2: prog@2 {
477 #clock-cells = <0>;
478 reg = <2>;
479 interrupts = <AT91_PMC_PCKRDY(2)>;
480 };
481 };
482
483 smd: smdclk {
484 compatible = "atmel,at91sam9x5-clk-smd";
485 #clock-cells = <0>;
486 clocks = <&plladiv>, <&utmi>;
487 };
488
489 systemck {
490 compatible = "atmel,at91rm9200-clk-system";
491 #address-cells = <1>;
492 #size-cells = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]493 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]494
495 ddrck: ddrck@2 {
496 #clock-cells = <0>;
497 reg = <2>;
498 clocks = <&mck>;
499 };
500
501 lcdck: lcdck@3 {
502 #clock-cells = <0>;
503 reg = <3>;
504 clocks = <&mck>;
505 };
506
507 smdck: smdck@4 {
508 #clock-cells = <0>;
509 reg = <4>;
510 clocks = <&smd>;
511 };
512
513 uhpck: uhpcki@6 {
514 #clock-cells = <0>;
515 reg = <6>;
516 clocks = <&usb>;
517 };
518
519 udpck: udpck@7 {
520 #clock-cells = <0>;
521 reg = <7>;
522 clocks = <&usb>;
523 };
524
525 pck0: pck0@8 {
526 #clock-cells = <0>;
527 reg = <8>;
528 clocks = <&prog0>;
529 };
530
531 pck1: pck1@9 {
532 #clock-cells = <0>;
533 reg = <9>;
534 clocks = <&prog1>;
535 };
536
537 pck2: pck2@10 {
538 #clock-cells = <0>;
539 reg = <10>;
540 clocks = <&prog2>;
541 };
542 };
543
544 periph32ck {
545 compatible = "atmel,at91sam9x5-clk-peripheral";
546 #address-cells = <1>;
547 #size-cells = <0>;
548 clocks = <&h32ck>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]549 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]550
551 pioD_clk: pioD_clk@5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]552 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]553 #clock-cells = <0>;
554 reg = <5>;
555 };
556
557 usart0_clk: usart0_clk@6 {
558 #clock-cells = <0>;
559 reg = <6>;
560 };
561
562 usart1_clk: usart1_clk@7 {
563 #clock-cells = <0>;
564 reg = <7>;
565 };
566
567 icm_clk: icm_clk@9 {
568 #clock-cells = <0>;
569 reg = <9>;
570 };
571
572 aes_clk: aes_clk@12 {
573 #clock-cells = <0>;
574 reg = <12>;
575 };
576
577 tdes_clk: tdes_clk@14 {
578 #clock-cells = <0>;
579 reg = <14>;
580 };
581
582 sha_clk: sha_clk@15 {
583 #clock-cells = <0>;
584 reg = <15>;
585 };
586
587 matrix1_clk: matrix1_clk@17 {
588 #clock-cells = <0>;
589 reg = <17>;
590 };
591
592 hsmc_clk: hsmc_clk@22 {
593 #clock-cells = <0>;
594 reg = <22>;
595 };
596
597 pioA_clk: pioA_clk@23 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]598 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]599 #clock-cells = <0>;
600 reg = <23>;
601 };
602
603 pioB_clk: pioB_clk@24 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]604 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]605 #clock-cells = <0>;
606 reg = <24>;
607 };
608
609 pioC_clk: pioC_clk@25 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]610 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]611 #clock-cells = <0>;
612 reg = <25>;
613 };
614
615 pioE_clk: pioE_clk@26 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]616 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]617 #clock-cells = <0>;
618 reg = <26>;
619 };
620
621 uart0_clk: uart0_clk@27 {
622 #clock-cells = <0>;
623 reg = <27>;
624 };
625
626 uart1_clk: uart1_clk@28 {
627 #clock-cells = <0>;
628 reg = <28>;
629 };
630
631 usart2_clk: usart2_clk@29 {
632 #clock-cells = <0>;
633 reg = <29>;
634 };
635
636 usart3_clk: usart3_clk@30 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]637 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]638 #clock-cells = <0>;
639 reg = <30>;
640 };
641
642 usart4_clk: usart4_clk@31 {
643 #clock-cells = <0>;
644 reg = <31>;
645 };
646
647 twi0_clk: twi0_clk@32 {
648 reg = <32>;
649 #clock-cells = <0>;
650 };
651
652 twi1_clk: twi1_clk@33 {
653 #clock-cells = <0>;
654 reg = <33>;
655 };
656
657 twi2_clk: twi2_clk@34 {
658 #clock-cells = <0>;
659 reg = <34>;
660 };
661
662 mci0_clk: mci0_clk@35 {
663 #clock-cells = <0>;
664 reg = <35>;
665 };
666
667 mci1_clk: mci1_clk@36 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]668 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]669 #clock-cells = <0>;
670 reg = <36>;
671 };
672
673 spi0_clk: spi0_clk@37 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]674 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]675 #clock-cells = <0>;
676 reg = <37>;
677 };
678
679 spi1_clk: spi1_clk@38 {
680 #clock-cells = <0>;
681 reg = <38>;
682 };
683
684 spi2_clk: spi2_clk@39 {
685 #clock-cells = <0>;
686 reg = <39>;
687 };
688
689 tcb0_clk: tcb0_clk@40 {
690 #clock-cells = <0>;
691 reg = <40>;
692 };
693
694 tcb1_clk: tcb1_clk@41 {
695 #clock-cells = <0>;
696 reg = <41>;
697 };
698
699 tcb2_clk: tcb2_clk@42 {
700 #clock-cells = <0>;
701 reg = <42>;
702 };
703
704 pwm_clk: pwm_clk@43 {
705 #clock-cells = <0>;
706 reg = <43>;
707 };
708
709 adc_clk: adc_clk@44 {
710 #clock-cells = <0>;
711 reg = <44>;
712 };
713
714 dbgu_clk: dbgu_clk@45 {
715 #clock-cells = <0>;
716 reg = <45>;
717 };
718
719 uhphs_clk: uhphs_clk@46 {
720 #clock-cells = <0>;
721 reg = <46>;
722 };
723
724 udphs_clk: udphs_clk@47 {
725 #clock-cells = <0>;
726 reg = <47>;
727 };
728
729 ssc0_clk: ssc0_clki@48 {
730 #clock-cells = <0>;
731 reg = <48>;
732 };
733
734 ssc1_clk: ssc1_clk@49 {
735 #clock-cells = <0>;
736 reg = <49>;
737 };
738
739 trng_clk: trng_clk@53 {
740 #clock-cells = <0>;
741 reg = <53>;
742 };
743
744 macb0_clk: macb0_clk@54 {
745 #clock-cells = <0>;
746 reg = <54>;
747 };
748
749 macb1_clk: macb1_clk@55 {
750 #clock-cells = <0>;
751 reg = <55>;
752 };
753
754 fuse_clk: fuse_clk@57 {
755 #clock-cells = <0>;
756 reg = <57>;
757 };
758
759 securam_clk: securam_clk@59 {
760 #clock-cells = <0>;
761 reg = <59>;
762 };
763
764 smd_clk: smd_clk@61 {
765 #clock-cells = <0>;
766 reg = <61>;
767 };
768
769 twi3_clk: twi3_clk@62 {
770 #clock-cells = <0>;
771 reg = <62>;
772 };
773
774 catb_clk: catb_clk@63 {
775 #clock-cells = <0>;
776 reg = <63>;
777 };
778 };
779
780 periph64ck {
781 compatible = "atmel,at91sam9x5-clk-peripheral";
782 #address-cells = <1>;
783 #size-cells = <0>;
784 clocks = <&mck>;
785
786 dma0_clk: dma0_clk@8 {
787 #clock-cells = <0>;
788 reg = <8>;
789 };
790
791 cpkcc_clk: cpkcc_clk@10 {
792 #clock-cells = <0>;
793 reg = <10>;
794 };
795
796 aesb_clk: aesb_clk@13 {
797 #clock-cells = <0>;
798 reg = <13>;
799 };
800
801 mpddr_clk: mpddr_clk@16 {
802 #clock-cells = <0>;
803 reg = <16>;
804 };
805
806 matrix0_clk: matrix0_clk@18 {
807 #clock-cells = <0>;
808 reg = <18>;
809 };
810
811 vdec_clk: vdec_clk@19 {
812 #clock-cells = <0>;
813 reg = <19>;
814 };
815
816 dma1_clk: dma1_clk@50 {
817 #clock-cells = <0>;
818 reg = <50>;
819 };
820
821 lcdc_clk: lcdc_clk@51 {
822 #clock-cells = <0>;
823 reg = <51>;
824 };
825
826 isi_clk: isi_clk@52 {
827 #clock-cells = <0>;
828 reg = <52>;
829 };
830 };
831 };
832
833 mmc0: mmc@f8000000 {
834 compatible = "atmel,hsmci";
835 reg = <0xf8000000 0x600>;
836 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
837 dmas = <&dma1
838 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
839 | AT91_XDMAC_DT_PERID(0))>;
840 dma-names = "rxtx";
841 pinctrl-names = "default";
842 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
843 status = "disabled";
844 #address-cells = <1>;
845 #size-cells = <0>;
846 clocks = <&mci0_clk>;
847 clock-names = "mci_clk";
848 };
849
850 uart0: serial@f8004000 {
851 compatible = "atmel,at91sam9260-usart";
852 reg = <0xf8004000 0x100>;
853 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
854 dmas = <&dma1
855 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
856 | AT91_XDMAC_DT_PERID(22))>,
857 <&dma1
858 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
859 | AT91_XDMAC_DT_PERID(23))>;
860 dma-names = "tx", "rx";
861 pinctrl-names = "default";
862 pinctrl-0 = <&pinctrl_uart0>;
863 clocks = <&uart0_clk>;
864 clock-names = "usart";
865 status = "disabled";
866 };
867
868 ssc0: ssc@f8008000 {
869 compatible = "atmel,at91sam9g45-ssc";
870 reg = <0xf8008000 0x4000>;
871 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
872 pinctrl-names = "default";
873 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
874 dmas = <&dma1
875 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
876 | AT91_XDMAC_DT_PERID(26))>,
877 <&dma1
878 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
879 | AT91_XDMAC_DT_PERID(27))>;
880 dma-names = "tx", "rx";
881 clocks = <&ssc0_clk>;
882 clock-names = "pclk";
883 status = "disabled";
884 };
885
886 pwm0: pwm@f800c000 {
887 compatible = "atmel,sama5d3-pwm";
888 reg = <0xf800c000 0x300>;
889 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
890 #pwm-cells = <3>;
891 clocks = <&pwm_clk>;
892 status = "disabled";
893 };
894
895 spi0: spi@f8010000 {
896 #address-cells = <1>;
897 #size-cells = <0>;
898 compatible = "atmel,at91rm9200-spi";
899 reg = <0xf8010000 0x100>;
900 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
901 dmas = <&dma1
902 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
903 | AT91_XDMAC_DT_PERID(10))>,
904 <&dma1
905 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
906 | AT91_XDMAC_DT_PERID(11))>;
907 dma-names = "tx", "rx";
908 pinctrl-names = "default";
909 pinctrl-0 = <&pinctrl_spi0>;
910 clocks = <&spi0_clk>;
911 clock-names = "spi_clk";
912 status = "disabled";
913 };
914
915 i2c0: i2c@f8014000 {
916 compatible = "atmel,sama5d4-i2c";
917 reg = <0xf8014000 0x4000>;
918 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
919 dmas = <&dma1
920 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
921 | AT91_XDMAC_DT_PERID(2))>,
922 <&dma1
923 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
924 | AT91_XDMAC_DT_PERID(3))>;
925 dma-names = "tx", "rx";
926 pinctrl-names = "default";
927 pinctrl-0 = <&pinctrl_i2c0>;
928 #address-cells = <1>;
929 #size-cells = <0>;
930 clocks = <&twi0_clk>;
931 status = "disabled";
932 };
933
934 i2c1: i2c@f8018000 {
935 compatible = "atmel,sama5d4-i2c";
936 reg = <0xf8018000 0x4000>;
937 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
938 dmas = <&dma1
939 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
940 | AT91_XDMAC_DT_PERID(4))>,
941 <&dma1
942 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
943 | AT91_XDMAC_DT_PERID(5))>;
944 dma-names = "tx", "rx";
945 pinctrl-names = "default";
946 pinctrl-0 = <&pinctrl_i2c1>;
947 #address-cells = <1>;
948 #size-cells = <0>;
949 clocks = <&twi1_clk>;
950 status = "disabled";
951 };
952
953 tcb0: timer@f801c000 {
954 compatible = "atmel,at91sam9x5-tcb";
955 reg = <0xf801c000 0x100>;
956 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
957 clocks = <&tcb0_clk>, <&clk32k>;
958 clock-names = "t0_clk", "slow_clk";
959 };
960
961 macb0: ethernet@f8020000 {
962 compatible = "atmel,sama5d4-gem";
963 reg = <0xf8020000 0x100>;
964 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
965 pinctrl-names = "default";
966 pinctrl-0 = <&pinctrl_macb0_rmii>;
967 #address-cells = <1>;
968 #size-cells = <0>;
969 clocks = <&macb0_clk>, <&macb0_clk>;
970 clock-names = "hclk", "pclk";
971 status = "disabled";
972 };
973
974 i2c2: i2c@f8024000 {
975 compatible = "atmel,sama5d4-i2c";
976 reg = <0xf8024000 0x4000>;
977 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
978 dmas = <&dma1
979 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
980 | AT91_XDMAC_DT_PERID(6))>,
981 <&dma1
982 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
983 | AT91_XDMAC_DT_PERID(7))>;
984 dma-names = "tx", "rx";
985 pinctrl-names = "default";
986 pinctrl-0 = <&pinctrl_i2c2>;
987 #address-cells = <1>;
988 #size-cells = <0>;
989 clocks = <&twi2_clk>;
990 status = "disabled";
991 };
992
993 sfr: sfr@f8028000 {
994 compatible = "atmel,sama5d4-sfr", "syscon";
995 reg = <0xf8028000 0x60>;
996 };
997
998 usart0: serial@f802c000 {
999 compatible = "atmel,at91sam9260-usart";
1000 reg = <0xf802c000 0x100>;
1001 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
1002 dmas = <&dma0
1003 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1004 | AT91_XDMAC_DT_PERID(36))>,
1005 <&dma0
1006 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1007 | AT91_XDMAC_DT_PERID(37))>;
1008 dma-names = "tx", "rx";
1009 pinctrl-names = "default";
1010 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
1011 clocks = <&usart0_clk>;
1012 clock-names = "usart";
1013 status = "disabled";
1014 };
1015
1016 usart1: serial@f8030000 {
1017 compatible = "atmel,at91sam9260-usart";
1018 reg = <0xf8030000 0x100>;
1019 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
1020 dmas = <&dma0
1021 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1022 | AT91_XDMAC_DT_PERID(38))>,
1023 <&dma0
1024 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1025 | AT91_XDMAC_DT_PERID(39))>;
1026 dma-names = "tx", "rx";
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
1029 clocks = <&usart1_clk>;
1030 clock-names = "usart";
1031 status = "disabled";
1032 };
1033
1034 mmc1: mmc@fc000000 {
1035 compatible = "atmel,hsmci";
1036 reg = <0xfc000000 0x600>;
1037 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1038 dmas = <&dma1
1039 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1040 | AT91_XDMAC_DT_PERID(1))>;
1041 dma-names = "rxtx";
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
1044 status = "disabled";
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 clocks = <&mci1_clk>;
1048 clock-names = "mci_clk";
1049 };
1050
1051 uart1: serial@fc004000 {
1052 compatible = "atmel,at91sam9260-usart";
1053 reg = <0xfc004000 0x100>;
1054 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
1055 dmas = <&dma1
1056 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1057 | AT91_XDMAC_DT_PERID(24))>,
1058 <&dma1
1059 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1060 | AT91_XDMAC_DT_PERID(25))>;
1061 dma-names = "tx", "rx";
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&pinctrl_uart1>;
1064 clocks = <&uart1_clk>;
1065 clock-names = "usart";
1066 status = "disabled";
1067 };
1068
1069 usart2: serial@fc008000 {
1070 compatible = "atmel,at91sam9260-usart";
1071 reg = <0xfc008000 0x100>;
1072 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
1073 dmas = <&dma1
1074 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1075 | AT91_XDMAC_DT_PERID(16))>,
1076 <&dma1
1077 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1078 | AT91_XDMAC_DT_PERID(17))>;
1079 dma-names = "tx", "rx";
1080 pinctrl-names = "default";
1081 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
1082 clocks = <&usart2_clk>;
1083 clock-names = "usart";
1084 status = "disabled";
1085 };
1086
1087 usart3: serial@fc00c000 {
1088 compatible = "atmel,at91sam9260-usart";
1089 reg = <0xfc00c000 0x100>;
1090 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
1091 dmas = <&dma1
1092 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1093 | AT91_XDMAC_DT_PERID(18))>,
1094 <&dma1
1095 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1096 | AT91_XDMAC_DT_PERID(19))>;
1097 dma-names = "tx", "rx";
1098 pinctrl-names = "default";
1099 pinctrl-0 = <&pinctrl_usart3>;
1100 clocks = <&usart3_clk>;
1101 clock-names = "usart";
1102 status = "disabled";
1103 };
1104
1105 usart4: serial@fc010000 {
1106 compatible = "atmel,at91sam9260-usart";
1107 reg = <0xfc010000 0x100>;
1108 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
1109 dmas = <&dma1
1110 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1111 | AT91_XDMAC_DT_PERID(20))>,
1112 <&dma1
1113 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1114 | AT91_XDMAC_DT_PERID(21))>;
1115 dma-names = "tx", "rx";
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&pinctrl_usart4>;
1118 clocks = <&usart4_clk>;
1119 clock-names = "usart";
1120 status = "disabled";
1121 };
1122
1123 ssc1: ssc@fc014000 {
1124 compatible = "atmel,at91sam9g45-ssc";
1125 reg = <0xfc014000 0x4000>;
1126 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
1127 pinctrl-names = "default";
1128 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1129 dmas = <&dma1
1130 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1131 | AT91_XDMAC_DT_PERID(28))>,
1132 <&dma1
1133 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1134 | AT91_XDMAC_DT_PERID(29))>;
1135 dma-names = "tx", "rx";
1136 clocks = <&ssc1_clk>;
1137 clock-names = "pclk";
1138 status = "disabled";
1139 };
1140
1141 spi1: spi@fc018000 {
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1144 compatible = "atmel,at91rm9200-spi";
1145 reg = <0xfc018000 0x100>;
1146 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
1147 dmas = <&dma1
1148 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1149 | AT91_XDMAC_DT_PERID(12))>,
1150 <&dma1
1151 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1152 | AT91_XDMAC_DT_PERID(13))>;
1153 dma-names = "tx", "rx";
1154 pinctrl-names = "default";
1155 pinctrl-0 = <&pinctrl_spi1>;
1156 clocks = <&spi1_clk>;
1157 clock-names = "spi_clk";
1158 status = "disabled";
1159 };
1160
1161 spi2: spi@fc01c000 {
1162 #address-cells = <1>;
1163 #size-cells = <0>;
1164 compatible = "atmel,at91rm9200-spi";
1165 reg = <0xfc01c000 0x100>;
1166 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
1167 dmas = <&dma1
1168 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1169 | AT91_XDMAC_DT_PERID(14))>,
1170 <&dma1
1171 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1172 | AT91_XDMAC_DT_PERID(15))>;
1173 dma-names = "tx", "rx";
1174 pinctrl-names = "default";
1175 pinctrl-0 = <&pinctrl_spi2>;
1176 clocks = <&spi2_clk>;
1177 clock-names = "spi_clk";
1178 status = "disabled";
1179 };
1180
1181 tcb1: timer@fc020000 {
1182 compatible = "atmel,at91sam9x5-tcb";
1183 reg = <0xfc020000 0x100>;
1184 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
1185 clocks = <&tcb1_clk>, <&clk32k>;
1186 clock-names = "t0_clk", "slow_clk";
1187 };
1188
1189 macb1: ethernet@fc028000 {
1190 compatible = "atmel,sama5d4-gem";
1191 reg = <0xfc028000 0x100>;
1192 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>;
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&pinctrl_macb1_rmii>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1197 clocks = <&macb1_clk>, <&macb1_clk>;
1198 clock-names = "hclk", "pclk";
1199 status = "disabled";
1200 };
1201
1202 trng@fc030000 {
1203 compatible = "atmel,at91sam9g45-trng";
1204 reg = <0xfc030000 0x100>;
1205 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
1206 clocks = <&trng_clk>;
1207 };
1208
1209 adc0: adc@fc034000 {
1210 compatible = "atmel,at91sam9x5-adc";
1211 reg = <0xfc034000 0x100>;
1212 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
1213 clocks = <&adc_clk>,
1214 <&adc_op_clk>;
1215 clock-names = "adc_clk", "adc_op_clk";
1216 atmel,adc-channels-used = <0x01f>;
1217 atmel,adc-startup-time = <40>;
1218 atmel,adc-use-external-triggers;
1219 atmel,adc-vref = <3000>;
1220 atmel,adc-res = <8 10>;
1221 atmel,adc-sample-hold-time = <11>;
1222 atmel,adc-res-names = "lowres", "highres";
1223 atmel,adc-ts-pressure-threshold = <10000>;
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1226 status = "disabled";
1227
1228 trigger@0 {
1229 trigger-name = "external-rising";
1230 trigger-value = <0x1>;
1231 trigger-external;
1232 reg = <0>;
1233 };
1234 trigger@1 {
1235 trigger-name = "external-falling";
1236 trigger-value = <0x2>;
1237 trigger-external;
1238 reg = <1>;
1239 };
1240 trigger@2 {
1241 trigger-name = "external-any";
1242 trigger-value = <0x3>;
1243 trigger-external;
1244 reg = <2>;
1245 };
1246 trigger@3 {
1247 trigger-name = "continuous";
1248 trigger-value = <0x6>;
1249 reg = <3>;
1250 };
1251 };
1252
1253 aes@fc044000 {
1254 compatible = "atmel,at91sam9g46-aes";
1255 reg = <0xfc044000 0x100>;
1256 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1257 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1258 | AT91_XDMAC_DT_PERID(41))>,
1259 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1260 | AT91_XDMAC_DT_PERID(40))>;
1261 dma-names = "tx", "rx";
1262 clocks = <&aes_clk>;
1263 clock-names = "aes_clk";
1264 status = "okay";
1265 };
1266
1267 tdes@fc04c000 {
1268 compatible = "atmel,at91sam9g46-tdes";
1269 reg = <0xfc04c000 0x100>;
1270 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
1271 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1272 | AT91_XDMAC_DT_PERID(42))>,
1273 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1274 | AT91_XDMAC_DT_PERID(43))>;
1275 dma-names = "tx", "rx";
1276 clocks = <&tdes_clk>;
1277 clock-names = "tdes_clk";
1278 status = "okay";
1279 };
1280
1281 sha@fc050000 {
1282 compatible = "atmel,at91sam9g46-sha";
1283 reg = <0xfc050000 0x100>;
1284 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
1285 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1286 | AT91_XDMAC_DT_PERID(44))>;
1287 dma-names = "tx";
1288 clocks = <&sha_clk>;
1289 clock-names = "sha_clk";
1290 status = "okay";
1291 };
1292
1293 rstc@fc068600 {
1294 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
1295 reg = <0xfc068600 0x10>;
1296 clocks = <&clk32k>;
1297 };
1298
1299 shdwc@fc068610 {
1300 compatible = "atmel,at91sam9x5-shdwc";
1301 reg = <0xfc068610 0x10>;
1302 clocks = <&clk32k>;
1303 };
1304
1305 pit: timer@fc068630 {
1306 compatible = "atmel,at91sam9260-pit";
1307 reg = <0xfc068630 0x10>;
1308 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1309 clocks = <&h32ck>;
1310 };
1311
1312 watchdog@fc068640 {
1313 compatible = "atmel,sama5d4-wdt";
1314 reg = <0xfc068640 0x10>;
1315 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1316 clocks = <&clk32k>;
1317 status = "disabled";
1318 };
1319
1320 sckc@fc068650 {
1321 compatible = "atmel,at91sam9x5-sckc";
1322 reg = <0xfc068650 0x4>;
1323
1324 slow_rc_osc: slow_rc_osc {
1325 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1326 #clock-cells = <0>;
1327 clock-frequency = <32768>;
1328 clock-accuracy = <250000000>;
1329 atmel,startup-time-usec = <75>;
1330 };
1331
1332 slow_osc: slow_osc {
1333 compatible = "atmel,at91sam9x5-clk-slow-osc";
1334 #clock-cells = <0>;
1335 clocks = <&slow_xtal>;
1336 atmel,startup-time-usec = <1200000>;
1337 };
1338
1339 clk32k: slowck {
1340 compatible = "atmel,at91sam9x5-clk-slow";
1341 #clock-cells = <0>;
1342 clocks = <&slow_rc_osc &slow_osc>;
1343 };
1344 };
1345
1346 rtc@fc0686b0 {
1347 compatible = "atmel,at91rm9200-rtc";
1348 reg = <0xfc0686b0 0x30>;
1349 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1350 clocks = <&clk32k>;
1351 };
1352
1353 dbgu: serial@fc069000 {
1354 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1355 reg = <0xfc069000 0x200>;
1356 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&pinctrl_dbgu>;
1359 clocks = <&dbgu_clk>;
1360 clock-names = "usart";
1361 status = "disabled";
1362 };
1363
1364 pioA: gpio@fc06a000 {
1365 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1366 reg = <0xfc06a000 0x100>;
1367 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1368 #gpio-cells = <2>;
1369 gpio-controller;
1370 interrupt-controller;
1371 #interrupt-cells = <2>;
1372 clocks = <&pioA_clk>;
1373 };
1374
1375 pioB: gpio@fc06b000 {
1376 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1377 reg = <0xfc06b000 0x100>;
1378 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1379 #gpio-cells = <2>;
1380 gpio-controller;
1381 interrupt-controller;
1382 #interrupt-cells = <2>;
1383 clocks = <&pioB_clk>;
1384 };
1385
1386 pioC: gpio@fc06c000 {
1387 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1388 reg = <0xfc06c000 0x100>;
1389 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1390 #gpio-cells = <2>;
1391 gpio-controller;
1392 interrupt-controller;
1393 #interrupt-cells = <2>;
1394 clocks = <&pioC_clk>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]1395 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]1396 };
1397
1398 pioD: gpio@fc068000 {
1399 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1400 reg = <0xfc068000 0x100>;
1401 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1402 #gpio-cells = <2>;
1403 gpio-controller;
1404 interrupt-controller;
1405 #interrupt-cells = <2>;
1406 clocks = <&pioD_clk>;
1407 };
1408
1409 pioE: gpio@fc06d000 {
1410 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1411 reg = <0xfc06d000 0x100>;
1412 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1413 #gpio-cells = <2>;
1414 gpio-controller;
1415 interrupt-controller;
1416 #interrupt-cells = <2>;
1417 clocks = <&pioE_clk>;
1418 };
1419
1420 pinctrl@fc06a000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]1421 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]1422 #address-cells = <1>;
1423 #size-cells = <1>;
1424 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1425 ranges = <0xfc068000 0xfc068000 0x100
1426 0xfc06a000 0xfc06a000 0x4000>;
1427 /* WARNING: revisit as pin spec has changed */
1428 atmel,mux-mask = <
1429 /* A B C */
1430 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1431 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1432 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1433 0x0003ff00 0x8002a800 0x00000000 /* pioD */
1434 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1435 >;
1436 reg = < 0xfc06a000 0x100
1437 0xfc06b000 0x100
1438 0xfc06c000 0x100
1439 0xfc068000 0x100
1440 0xfc06d000 0x100
1441 >;
1442
1443 /* pinctrl pin settings */
1444 adc0 {
1445 pinctrl_adc0_adtrg: adc0_adtrg {
1446 atmel,pins =
1447 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1448 };
1449 pinctrl_adc0_ad0: adc0_ad0 {
1450 atmel,pins =
1451 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1452 };
1453 pinctrl_adc0_ad1: adc0_ad1 {
1454 atmel,pins =
1455 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1456 };
1457 pinctrl_adc0_ad2: adc0_ad2 {
1458 atmel,pins =
1459 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1460 };
1461 pinctrl_adc0_ad3: adc0_ad3 {
1462 atmel,pins =
1463 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1464 };
1465 pinctrl_adc0_ad4: adc0_ad4 {
1466 atmel,pins =
1467 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1468 };
1469 };
1470
1471 dbgu {
1472 pinctrl_dbgu: dbgu-0 {
1473 atmel,pins =
1474 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1475 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1476 };
1477 };
1478
1479 i2c0 {
1480 pinctrl_i2c0: i2c0-0 {
1481 atmel,pins =
1482 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1483 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1484 };
1485 };
1486
1487 i2c1 {
1488 pinctrl_i2c1: i2c1-0 {
1489 atmel,pins =
1490 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1491 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1492 };
1493 };
1494
1495 i2c2 {
1496 pinctrl_i2c2: i2c2-0 {
1497 atmel,pins =
1498 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1499 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1500 };
1501 };
1502
1503 isi {
1504 pinctrl_isi_data_0_7: isi-0-data-0-7 {
1505 atmel,pins =
1506 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
1507 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
1508 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
1509 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
1510 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
1511 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
1512 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
1513 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
1514 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
1515 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
1516 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1517 };
1518 pinctrl_isi_data_8_9: isi-0-data-8-9 {
1519 atmel,pins =
1520 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1521 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1522 };
1523 pinctrl_isi_data_10_11: isi-0-data-10-11 {
1524 atmel,pins =
1525 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1526 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1527 };
1528 };
1529
1530 lcd {
1531 pinctrl_lcd_base: lcd-base-0 {
1532 atmel,pins =
1533 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
1534 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
1535 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
1536 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1537 };
1538 pinctrl_lcd_pwm: lcd-pwm-0 {
1539 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
1540 };
1541 pinctrl_lcd_rgb444: lcd-rgb-0 {
1542 atmel,pins =
1543 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1544 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1545 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1546 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1547 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1548 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1549 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1550 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1551 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1552 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1553 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1554 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1555 };
1556 pinctrl_lcd_rgb565: lcd-rgb-1 {
1557 atmel,pins =
1558 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1559 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1560 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1561 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1562 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1563 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1564 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1565 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1566 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1567 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1568 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1569 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1570 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1571 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1572 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1573 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1574 };
1575 pinctrl_lcd_rgb666: lcd-rgb-2 {
1576 atmel,pins =
1577 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1578 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1579 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1580 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1581 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1582 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1583 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1584 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1585 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1586 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1587 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1588 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1589 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1590 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1591 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1592 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1593 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1594 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1595 };
1596 pinctrl_lcd_rgb777: lcd-rgb-3 {
1597 atmel,pins =
1598 /* LCDDAT0 conflicts with TMS */
1599 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1600 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1601 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1602 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1603 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1604 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1605 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1606 /* LCDDAT8 conflicts with TCK */
1607 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1608 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1609 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1610 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1611 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1612 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1613 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1614 /* LCDDAT16 conflicts with NTRST */
1615 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1616 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1617 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1618 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1619 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1620 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1621 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1622 };
1623 pinctrl_lcd_rgb888: lcd-rgb-4 {
1624 atmel,pins =
1625 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1626 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1627 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1628 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1629 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1630 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1631 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1632 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1633 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1634 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1635 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1636 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1637 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1638 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1639 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1640 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1641 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
1642 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1643 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1644 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1645 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1646 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1647 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1648 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1649 };
1650 };
1651
1652 macb0 {
1653 pinctrl_macb0_rmii: macb0_rmii-0 {
1654 atmel,pins =
1655 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1656 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1657 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1658 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1659 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1660 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1661 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1662 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1663 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1664 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1665 >;
1666 };
1667 };
1668
1669 macb1 {
1670 pinctrl_macb1_rmii: macb1_rmii-0 {
1671 atmel,pins =
1672 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */
1673 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */
1674 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */
1675 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */
1676 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */
1677 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */
1678 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */
1679 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */
1680 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */
1681 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */
1682 >;
1683 };
1684 };
1685
1686 mmc0 {
1687 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1688 atmel,pins =
1689 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1690 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */
1691 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */
1692 >;
1693 };
1694 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1695 atmel,pins =
1696 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */
1697 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */
1698 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */
1699 >;
1700 };
1701 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
1702 atmel,pins =
1703 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */
1704 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */
1705 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */
1706 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */
1707 >;
1708 };
1709 };
1710
1711 mmc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]1712 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]1713 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]1714 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]1715 atmel,pins =
1716 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1717 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1718 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1719 >;
1720 };
1721 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]1722 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]1723 atmel,pins =
1724 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1725 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1726 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1727 >;
1728 };
1729 };
1730
1731 nand0 {
1732 pinctrl_nand: nand-0 {
1733 atmel,pins =
1734 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1735 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1736
1737 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1738 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1739
1740 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1741 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1742 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1743 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1744 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1745 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1746 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1747 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1748 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1749 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1750 };
1751 };
1752
1753 spi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]1754 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]1755 pinctrl_spi0: spi0-0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]1756 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]1757 atmel,pins =
1758 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1759 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1760 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1761 >;
1762 };
1763 };
1764
1765 ssc0 {
1766 pinctrl_ssc0_tx: ssc0_tx {
1767 atmel,pins =
1768 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
1769 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
1770 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1771 };
1772
1773 pinctrl_ssc0_rx: ssc0_rx {
1774 atmel,pins =
1775 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
1776 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
1777 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1778 };
1779 };
1780
1781 ssc1 {
1782 pinctrl_ssc1_tx: ssc1_tx {
1783 atmel,pins =
1784 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
1785 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
1786 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1787 };
1788
1789 pinctrl_ssc1_rx: ssc1_rx {
1790 atmel,pins =
1791 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
1792 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
1793 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1794 };
1795 };
1796
1797 spi1 {
1798 pinctrl_spi1: spi1-0 {
1799 atmel,pins =
1800 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */
1801 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */
1802 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */
1803 >;
1804 };
1805 };
1806
1807 spi2 {
1808 pinctrl_spi2: spi2-0 {
1809 atmel,pins =
1810 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */
1811 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */
1812 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */
1813 >;
1814 };
1815 };
1816
1817 uart0 {
1818 pinctrl_uart0: uart0-0 {
1819 atmel,pins =
1820 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1821 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1822 >;
1823 };
1824 };
1825
1826 uart1 {
1827 pinctrl_uart1: uart1-0 {
1828 atmel,pins =
1829 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_NONE /* RXD */
1830 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* TXD */
1831 >;
1832 };
1833 };
1834
1835 usart0 {
1836 pinctrl_usart0: usart0-0 {
1837 atmel,pins =
1838 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */
1839 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */
1840 >;
1841 };
1842 pinctrl_usart0_rts: usart0_rts-0 {
1843 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1844 };
1845 pinctrl_usart0_cts: usart0_cts-0 {
1846 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1847 };
1848 };
1849
1850 usart1 {
1851 pinctrl_usart1: usart1-0 {
1852 atmel,pins =
1853 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */
1854 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */
1855 >;
1856 };
1857 pinctrl_usart1_rts: usart1_rts-0 {
1858 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1859 };
1860 pinctrl_usart1_cts: usart1_cts-0 {
1861 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1862 };
1863 };
1864
1865 usart2 {
1866 pinctrl_usart2: usart2-0 {
1867 atmel,pins =
1868 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1869 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1870 >;
1871 };
1872 pinctrl_usart2_rts: usart2_rts-0 {
1873 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1874 };
1875 pinctrl_usart2_cts: usart2_cts-0 {
1876 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1877 };
1878 };
1879
1880 usart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]1881 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]1882 pinctrl_usart3: usart3-0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]1883 bootph-all;
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]1884 atmel,pins =
1885 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1886 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1887 >;
1888 };
1889 };
1890
1891 usart4 {
1892 pinctrl_usart4: usart4-0 {
1893 atmel,pins =
1894 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1895 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1896 >;
1897 };
1898 pinctrl_usart4_rts: usart4_rts-0 {
1899 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1900 };
1901 pinctrl_usart4_cts: usart4_cts-0 {
1902 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1903 };
1904 };
1905 };
1906
1907 aic: interrupt-controller@fc06e000 {
1908 #interrupt-cells = <3>;
1909 compatible = "atmel,sama5d4-aic";
1910 interrupt-controller;
1911 reg = <0xfc06e000 0x200>;
1912 atmel,external-irqs = <56>;
1913 };
1914 };
1915 };
Eugen Hristeveffb40b2018-09-18 10:35:57 +0300[diff] [blame]1916
1917 onewire_tm: onewire {
1918 compatible = "w1-gpio";
1919 status = "disabled";
1920 };
Wenyou Yang1a69b142017-03-24 09:18:43 +0800[diff] [blame]1921};