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git01.mediatek.com / filogic / uboot / cefdc034bbf172d12e1278e478ee28f2f0241d0c / . / arch / arm / dts / k3-j721s2-common-proc-board-u-boot.dtsi
blob: 4fd6d364175d49fe49d8ac72115a849c78b25474 [file] [log] [blame]
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/ {
7 chosen {
8 stdout-path = "serial2:115200n8";
9 tick-timer = &timer1;
10 };
11
12 aliases {
13 serial0 = &wkup_uart0;
14 serial1 = &mcu_uart0;
15 serial2 = &main_uart8;
16 i2c0 = &wkup_i2c0;
17 i2c1 = &mcu_i2c0;
18 i2c2 = &mcu_i2c1;
19 i2c3 = &main_i2c0;
20 ethernet0 = &cpsw_port1;
21 };
22};
23
24&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]26};
27
28&cbass_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]30};
31
32&main_navss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]34};
35
36&cbass_mcu_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]38
39 timer1: timer@40400000 {
40 compatible = "ti,omap5430-timer";
41 reg = <0x0 0x40400000 0x0 0x80>;
42 ti,timer-alwon;
Vignesh Raghavendra36a8b052022-03-07 14:55:51 +0530[diff] [blame]43 clock-frequency = <250000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]45 };
46
47 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]49 };
50};
51
52&mcu_navss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]54};
55
56&mcu_ringacc {
57 reg = <0x0 0x2b800000 0x0 0x400000>,
58 <0x0 0x2b000000 0x0 0x400000>,
59 <0x0 0x28590000 0x0 0x100>,
60 <0x0 0x2a500000 0x0 0x40000>,
61 <0x0 0x28440000 0x0 0x40000>;
62 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]64};
65
66&mcu_udmap {
67 reg = <0x0 0x285c0000 0x0 0x100>,
68 <0x0 0x284c0000 0x0 0x4000>,
69 <0x0 0x2a800000 0x0 0x40000>,
70 <0x0 0x284a0000 0x0 0x4000>,
71 <0x0 0x2aa00000 0x0 0x40000>,
72 <0x0 0x28400000 0x0 0x2000>;
73 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
74 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]76};
77
78&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]80};
81
82&sms {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]84 k3_sysreset: sysreset-controller {
85 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]87 };
88};
89
90&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]92};
93
94&main_uart8_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]96};
97
98&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]100};
101
102&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]104};
105
106&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]108};
109
110&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]112};
113
114&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]116};
117
118&main_uart8 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]119 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]120};
121
122&mcu_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]123 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]124};
125
126&wkup_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]128};
129
130&mcu_cpsw {
131 reg = <0x0 0x46000000 0x0 0x200000>,
132 <0x0 0x40f00200 0x0 0x8>;
133 reg-names = "cpsw_nuss", "mac_efuse";
134 /delete-property/ ranges;
135
136 cpsw-phy-sel@40f04040 {
137 compatible = "ti,am654-cpsw-phy-sel";
138 reg= <0x0 0x40f04040 0x0 0x4>;
139 reg-names = "gmii-sel";
140 };
141};
142
143&main_sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]144 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]145};
146
147&main_sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]148 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]149};