Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ |
| 4 | */ |
| 5 | |
| 6 | /dts-v1/; |
| 7 | |
| 8 | #include "k3-am68-sk-som.dtsi" |
| 9 | #include "k3-j721s2-ddr-evm-lp4-4266.dtsi" |
| 10 | #include "k3-j721s2-ddr.dtsi" |
| 11 | |
| 12 | / { |
| 13 | chosen { |
| 14 | firmware-loader = &fs_loader0; |
| 15 | stdout-path = &main_uart8; |
| 16 | tick-timer = &timer1; |
| 17 | }; |
| 18 | |
| 19 | aliases { |
| 20 | remoteproc0 = &sysctrler; |
| 21 | remoteproc1 = &a72_0; |
| 22 | }; |
| 23 | |
| 24 | fs_loader0: fs_loader@0 { |
| 25 | compatible = "u-boot,fs-loader"; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 26 | bootph-all; |
Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 27 | }; |
| 28 | |
| 29 | a72_0: a72@0 { |
| 30 | compatible = "ti,am654-rproc"; |
| 31 | reg = <0x0 0x00a90000 0x0 0x10>; |
| 32 | power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, |
| 33 | <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; |
| 34 | resets = <&k3_reset 202 0>; |
| 35 | clocks = <&k3_clks 61 1>; |
| 36 | assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; |
| 37 | assigned-clock-parents = <&k3_clks 61 2>; |
| 38 | assigned-clock-rates = <200000000>, <2000000000>; |
| 39 | ti,sci = <&sms>; |
| 40 | ti,sci-proc-id = <32>; |
| 41 | ti,sci-host-id = <10>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 42 | bootph-pre-ram; |
Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 43 | }; |
| 44 | |
| 45 | clk_200mhz: dummy_clock_200mhz { |
| 46 | compatible = "fixed-clock"; |
| 47 | #clock-cells = <0>; |
| 48 | clock-frequency = <200000000>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 49 | bootph-pre-ram; |
Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | clk_19_2mhz: dummy_clock_19_2mhz { |
| 53 | compatible = "fixed-clock"; |
| 54 | #clock-cells = <0>; |
| 55 | clock-frequency = <19200000>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 56 | bootph-pre-ram; |
Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 57 | }; |
| 58 | }; |
| 59 | |
| 60 | &cbass_mcu_wakeup { |
| 61 | sa3_secproxy: secproxy@44880000 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 62 | bootph-pre-ram; |
Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 63 | compatible = "ti,am654-secure-proxy"; |
| 64 | reg = <0x0 0x44880000 0x0 0x20000>, |
| 65 | <0x0 0x44860000 0x0 0x20000>, |
| 66 | <0x0 0x43600000 0x0 0x10000>; |
| 67 | reg-names = "rt", "scfg", "target_data"; |
| 68 | #mbox-cells = <1>; |
| 69 | }; |
| 70 | |
| 71 | mcu_secproxy: secproxy@2a380000 { |
| 72 | compatible = "ti,am654-secure-proxy"; |
| 73 | reg = <0x0 0x2a380000 0x0 0x80000>, |
| 74 | <0x0 0x2a400000 0x0 0x80000>, |
| 75 | <0x0 0x2a480000 0x0 0x80000>; |
| 76 | reg-names = "rt", "scfg", "target_data"; |
| 77 | #mbox-cells = <1>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 78 | bootph-pre-ram; |
Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 79 | }; |
| 80 | |
| 81 | sysctrler: sysctrler { |
| 82 | compatible = "ti,am654-system-controller"; |
| 83 | mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>; |
| 84 | mbox-names = "tx", "rx", "boot_notify"; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 85 | bootph-pre-ram; |
Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 86 | }; |
| 87 | |
| 88 | dm_tifs: dm-tifs { |
| 89 | compatible = "ti,j721e-dm-sci"; |
| 90 | ti,host-id = <3>; |
| 91 | ti,secure-host; |
| 92 | mbox-names = "rx", "tx"; |
| 93 | mboxes= <&mcu_secproxy 21>, |
| 94 | <&mcu_secproxy 23>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 95 | bootph-pre-ram; |
Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 96 | }; |
| 97 | }; |
| 98 | |
| 99 | &main_pmx0 { |
| 100 | main_uart8_pins_default: main-uart8-pins-default { |
| 101 | pinctrl-single,pins = < |
| 102 | J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ |
| 103 | J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ |
| 104 | >; |
| 105 | }; |
| 106 | |
| 107 | main_mmc1_pins_default: main-mmc1-pins-default { |
| 108 | pinctrl-single,pins = < |
| 109 | J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ |
| 110 | J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ |
| 111 | J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ |
| 112 | J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ |
| 113 | J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ |
| 114 | J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ |
| 115 | J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ |
| 116 | J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ |
| 117 | >; |
| 118 | }; |
| 119 | |
| 120 | main_usbss0_pins_default: main-usbss0-pins-default { |
| 121 | pinctrl-single,pins = < |
| 122 | J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ |
| 123 | >; |
| 124 | }; |
| 125 | }; |
| 126 | |
| 127 | &wkup_pmx0 { |
| 128 | mcu_uart0_pins_default: mcu-uart0-pins-default { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 129 | bootph-pre-ram; |
Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 130 | pinctrl-single,pins = < |
| 131 | J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /*(C24) WKUP_GPIO0_13.MCU_UART0_RXD*/ |
| 132 | J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /*(C25) WKUP_GPIO0_12.MCU_UART0_TXD*/ |
| 133 | >; |
| 134 | }; |
| 135 | |
| 136 | wkup_uart0_pins_default: wkup-uart0-pins-default { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 137 | bootph-pre-ram; |
Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 138 | pinctrl-single,pins = < |
| 139 | J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /*(E25) WKUP_GPIO0_6.WKUP_UART0_CTSn*/ |
| 140 | J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /*(F28) WKUP_GPIO0_7.WKUP_UART0_RTSn*/ |
| 141 | J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ |
| 142 | J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ |
| 143 | >; |
| 144 | }; |
| 145 | |
| 146 | }; |
| 147 | |
| 148 | &sms { |
| 149 | mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; |
| 150 | mbox-names = "tx", "rx", "notify"; |
| 151 | ti,host-id = <4>; |
| 152 | ti,secure-host; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 153 | bootph-pre-ram; |
Sinthu Raja | 9ab2ac4 | 2023-01-10 21:17:57 +0530 | [diff] [blame] | 154 | }; |
| 155 | |
| 156 | &wkup_uart0 { |
| 157 | pinctrl-names = "default"; |
| 158 | pinctrl-0 = <&wkup_uart0_pins_default>; |
| 159 | }; |
| 160 | |
| 161 | &mcu_uart0 { |
| 162 | pinctrl-names = "default"; |
| 163 | pinctrl-0 = <&mcu_uart0_pins_default>; |
| 164 | }; |
| 165 | |
| 166 | &main_uart8 { |
| 167 | pinctrl-names = "default"; |
| 168 | pinctrl-0 = <&main_uart8_pins_default>; |
| 169 | }; |
| 170 | |
| 171 | &main_sdhci0 { |
| 172 | status = "disabled"; |
| 173 | }; |
| 174 | |
| 175 | &main_sdhci1 { |
| 176 | /delete-property/ power-domains; |
| 177 | /delete-property/ assigned-clocks; |
| 178 | /delete-property/ assigned-clock-parents; |
| 179 | pinctrl-0 = <&main_mmc1_pins_default>; |
| 180 | pinctrl-names = "default"; |
| 181 | clock-names = "clk_xin"; |
| 182 | clocks = <&clk_200mhz>; |
| 183 | ti,driver-strength-ohm = <50>; |
| 184 | }; |
| 185 | |
| 186 | &mcu_ringacc { |
| 187 | ti,sci = <&dm_tifs>; |
| 188 | }; |
| 189 | |
| 190 | &mcu_udmap { |
| 191 | ti,sci = <&dm_tifs>; |
| 192 | }; |
| 193 | |
| 194 | #include "k3-am68-sk-base-board-u-boot.dtsi" |