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git01.mediatek.com / filogic / uboot / cefdc034bbf172d12e1278e478ee28f2f0241d0c / . / arch / arm / dts / imx93-11x11-evk.dts
blob: b3a5a3d71e249c3506341e58715448ae71f95522 [file] [log] [blame]
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 NXP
4 */
5
6/dts-v1/;
7
8#include "imx93.dtsi"
9
10/{
11 chosen {
12 stdout-path = &lpuart1;
13 };
14
15 reserved-memory {
16 #address-cells = <2>;
17 #size-cells = <2>;
18 ranges;
19
20 audio: audio@a4120000 {
21 compatible = "shared-dma-pool";
22 reg = <0 0xa4120000 0 0x100000>;
23 no-map;
24 };
25 };
26
27 reg_can2_stby: regulator-can2-stby {
28 compatible = "regulator-fixed";
29 regulator-name = "can2-stby";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>;
33 enable-active-low;
34 };
35
36 reg_usdhc2_vmmc: regulator-usdhc2 {
37 compatible = "regulator-fixed";
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
40 regulator-name = "VSD_3V3";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
44 enable-active-high;
45 };
46
47 usdhc3_pwrseq: usdhc3_pwrseq {
48 compatible = "mmc-pwrseq-simple";
49 reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
50 };
51
52 reg_vref_1v8: regulator-adc-vref {
53 compatible = "regulator-fixed";
54 regulator-name = "vref_1v8";
55 regulator-min-microvolt = <1800000>;
56 regulator-max-microvolt = <1800000>;
57 };
58
59};
60
61&lpi2c1 {
62 #address-cells = <1>;
63 #size-cells = <0>;
64 clock-frequency = <400000>;
65 pinctrl-names = "default", "sleep";
66 pinctrl-0 = <&pinctrl_lpi2c1>;
67 pinctrl-1 = <&pinctrl_lpi2c1>;
68 status = "okay";
69
70 ptn5110: tcpc@50 {
71 compatible = "nxp,ptn5110";
72 reg = <0x50>;
73 interrupt-parent = <&pcal6524>;
74 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
75 status = "okay";
76
77 port {
78 typec1_dr_sw: endpoint {
79 remote-endpoint = <&usb1_drd_sw>;
80 };
81 };
82
83 typec1_con: connector {
84 compatible = "usb-c-connector";
85 label = "USB-C";
86 power-role = "dual";
87 data-role = "dual";
88 try-power-role = "sink";
89 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
90 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
91 PDO_VAR(5000, 20000, 3000)>;
92 op-sink-microwatt = <15000000>;
93 self-powered;
94 };
95 };
96
97 ptn5110_2: tcpc@51 {
98 compatible = "nxp,ptn5110";
99 reg = <0x51>;
100 interrupt-parent = <&pcal6524>;
101 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
102 status = "okay";
103
104 port {
105 typec2_dr_sw: endpoint {
106 remote-endpoint = <&usb2_drd_sw>;
107 };
108 };
109
110 typec2_con: connector {
111 compatible = "usb-c-connector";
112 label = "USB-C";
113 power-role = "dual";
114 data-role = "dual";
115 try-power-role = "sink";
116 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
117 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
118 PDO_VAR(5000, 20000, 3000)>;
119 op-sink-microwatt = <15000000>;
120 self-powered;
121 };
122 };
123};
124
125&lpi2c2 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 clock-frequency = <400000>;
129 pinctrl-names = "default", "sleep";
130 pinctrl-0 = <&pinctrl_lpi2c2>;
131 pinctrl-1 = <&pinctrl_lpi2c2>;
132 status = "okay";
133
134 pmic@25 {
135 compatible = "nxp,pca9451a";
136 reg = <0x25>;
137 pinctrl-names = "default";
138 interrupt-parent = <&pcal6524>;
139 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
140
141 regulators {
142 buck1: BUCK1 {
143 regulator-name = "BUCK1";
144 regulator-min-microvolt = <600000>;
145 regulator-max-microvolt = <2187500>;
146 regulator-boot-on;
147 regulator-always-on;
148 regulator-ramp-delay = <3125>;
149 };
150
151 buck2: BUCK2 {
152 regulator-name = "BUCK2";
153 regulator-min-microvolt = <600000>;
154 regulator-max-microvolt = <2187500>;
155 regulator-boot-on;
156 regulator-always-on;
157 regulator-ramp-delay = <3125>;
158 };
159
160 buck4: BUCK4{
161 regulator-name = "BUCK4";
162 regulator-min-microvolt = <600000>;
163 regulator-max-microvolt = <3400000>;
164 regulator-boot-on;
165 regulator-always-on;
166 };
167
168 buck5: BUCK5{
169 regulator-name = "BUCK5";
170 regulator-min-microvolt = <600000>;
171 regulator-max-microvolt = <3400000>;
172 regulator-boot-on;
173 regulator-always-on;
174 };
175
176 buck6: BUCK6 {
177 regulator-name = "BUCK6";
178 regulator-min-microvolt = <600000>;
179 regulator-max-microvolt = <3400000>;
180 regulator-boot-on;
181 regulator-always-on;
182 };
183
184 ldo1: LDO1 {
185 regulator-name = "LDO1";
186 regulator-min-microvolt = <1600000>;
187 regulator-max-microvolt = <3300000>;
188 regulator-boot-on;
189 regulator-always-on;
190 };
191
192 ldo2: LDO2 {
193 regulator-name = "LDO2";
194 regulator-min-microvolt = <800000>;
195 regulator-max-microvolt = <1150000>;
196 regulator-boot-on;
197 regulator-always-on;
198 };
199
200 ldo3: LDO3 {
201 regulator-name = "LDO3";
202 regulator-min-microvolt = <800000>;
203 regulator-max-microvolt = <3300000>;
204 regulator-boot-on;
205 regulator-always-on;
206 };
207
208 ldo4: LDO4 {
209 regulator-name = "LDO4";
210 regulator-min-microvolt = <800000>;
211 regulator-max-microvolt = <3300000>;
212 regulator-boot-on;
213 regulator-always-on;
214 };
215
216 ldo5: LDO5 {
217 regulator-name = "LDO5";
218 regulator-min-microvolt = <1800000>;
219 regulator-max-microvolt = <3300000>;
220 regulator-boot-on;
221 regulator-always-on;
222 };
223 };
224 };
225
226 pcal6524: gpio@22 {
227 compatible = "nxp,pcal6524";
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_pcal6524>;
230 reg = <0x22>;
231 gpio-controller;
232 #gpio-cells = <2>;
233 interrupt-controller;
234 #interrupt-cells = <2>;
235 interrupt-parent = <&gpio3>;
236 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
237 };
238
239 adp5585gpio: gpio@34 {
240 compatible = "adp5585";
241 reg = <0x34>;
242 gpio-controller;
243 #gpio-cells = <2>;
244 };
245};
246
247&lpuart1 { /* console */
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_uart1>;
250 status = "okay";
251};
252
253&lpuart2 {
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart2>;
256 status = "disabled";
257};
258
259&usbotg1 {
260 dr_mode = "otg";
261 hnp-disable;
262 srp-disable;
263 adp-disable;
264 usb-role-switch;
265 disable-over-current;
266 samsung,picophy-pre-emp-curr-control = <3>;
267 samsung,picophy-dc-vol-level-adjust = <7>;
268 status = "okay";
269
270 port {
271 usb1_drd_sw: endpoint {
272 remote-endpoint = <&typec1_dr_sw>;
273 };
274 };
275};
276
277&usbotg2 {
278 dr_mode = "otg";
279 hnp-disable;
280 srp-disable;
281 adp-disable;
282 usb-role-switch;
283 disable-over-current;
284 samsung,picophy-pre-emp-curr-control = <3>;
285 samsung,picophy-dc-vol-level-adjust = <7>;
286 status = "okay";
287
288 port {
289 usb2_drd_sw: endpoint {
290 remote-endpoint = <&typec2_dr_sw>;
291 };
292 };
293};
294
295&usdhc1 {
296 pinctrl-names = "default", "state_100mhz", "state_200mhz";
297 pinctrl-0 = <&pinctrl_usdhc1>;
298 pinctrl-1 = <&pinctrl_usdhc1>;
299 pinctrl-2 = <&pinctrl_usdhc1>;
300 bus-width = <8>;
301 non-removable;
302 status = "okay";
303};
304
305&usdhc2 {
306 pinctrl-names = "default", "state_100mhz", "state_200mhz";
307 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
308 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
309 pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
310 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
311 vmmc-supply = <&reg_usdhc2_vmmc>;
312 bus-width = <4>;
313 status = "okay";
314 no-sdio;
315 no-mmc;
316};
317
318&usdhc3 {
319 status = "disabled";
320};
321
322&fec {
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_fec>;
325 phy-mode = "rgmii-id";
326 phy-handle = <&ethphy2>;
327 fsl,magic-packet;
328 status = "okay";
329
330 mdio {
331 #address-cells = <1>;
332 #size-cells = <0>;
333 clock-frequency = <5000000>;
334
335 ethphy2: ethernet-phy@2 {
336 compatible = "ethernet-phy-ieee802.3-c22";
337 reg = <2>;
338 eee-broken-1000t;
339 rtl821x,aldps-disable;
340 rtl821x,clkout-disable;
341 };
342 };
343};
344
345&eqos {
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_eqos>;
348 phy-mode = "rgmii-id";
349 phy-handle = <&ethphy1>;
350 status = "okay";
351
352 mdio {
353 compatible = "snps,dwmac-mdio";
354 #address-cells = <1>;
355 #size-cells = <0>;
356 clock-frequency = <5000000>;
357
358 ethphy1: ethernet-phy@1 {
359 compatible = "ethernet-phy-ieee802.3-c22";
360 reg = <1>;
361 eee-broken-1000t;
362 rtl821x,aldps-disable;
363 rtl821x,clkout-disable;
364 };
365 };
366};
367
368&flexspi {
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_flexspi>;
371 status = "disabled";
372
373 flash0: flash@0 {
374 reg = <0>;
375 #address-cells = <1>;
376 #size-cells = <1>;
377 compatible = "jedec,spi-nor";
378 spi-max-frequency = <80000000>;
379 spi-tx-bus-width = <1>;
380 spi-rx-bus-width = <1>;
381 };
382};
383
384&iomuxc {
385 pinctrl-names = "default";
386 status = "okay";
387
388 pinctrl_flexcan2: flexcan2grp {
389 fsl,pins = <
390 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
391 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
392 >;
393 };
394
395 pinctrl_flexspi: flexspigrp {
396 fsl,pins = <
397 MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42
398 MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x42
399 MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42
400 MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x42
401 MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42
402 MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42
403 MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42
404 MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42
405 MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x42
406 MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x42
407 MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x42
408 MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x42
409 >;
410 };
411
412 pinctrl_fec: fecgrp {
413 fsl,pins = <
414 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
415 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
416 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
417 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
418 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
419 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
420 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
421 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
422 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
423 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
424 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
425 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
426 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
427 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
428 >;
429 };
430
431 pinctrl_eqos: eqosgrp {
432 fsl,pins = <
433 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
434 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
435 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
436 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
437 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
438 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
439 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
440 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
441 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
442 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
443 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
444 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
445 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
446 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
447 >;
448 };
449
450 pinctrl_lpi2c1: lpi2c1grp {
451 fsl,pins = <
452 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
453 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
454 >;
455 };
456
457 pinctrl_lpi2c2: lpi2c2grp {
458 fsl,pins = <
459 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
460 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
461 >;
462 };
463
464 pinctrl_pcal6524: pcal6524grp {
465 fsl,pins = <
466 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
467 >;
468 };
469
470 pinctrl_uart1: uart1grp {
471 fsl,pins = <
472 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
473 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
474 >;
475 };
476
477 pinctrl_uart2: uart2grp {
478 fsl,pins = <
479 MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
480 MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
481 >;
482 };
483
484 pinctrl_usdhc1: usdhc1grp {
485 fsl,pins = <
486 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe
487 MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
488 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
489 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
490 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
491 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
492 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
493 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
494 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
495 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
496 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe
497 >;
498 };
499
500 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
501 fsl,pins = <
502 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
503 >;
504 };
505
506 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
507 fsl,pins = <
508 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
509 >;
510 };
511
512 pinctrl_usdhc2: usdhc2grp {
513 fsl,pins = <
514 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
515 MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
516 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
517 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
518 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
519 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
520 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
521 >;
522 };
523};
524
525&wdog3 {
526 status = "okay";
527};