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git01.mediatek.com / filogic / uboot / cefdc034bbf172d12e1278e478ee28f2f0241d0c / . / arch / arm / dts / imx8mn-var-som-symphony-u-boot.dtsi
blob: af80aaea0b8d68284ad7bd1fd5c95d252dc2970a [file] [log] [blame]
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2021 Collabora Ltd.
4 */
5
Adam Ford09e33912022-10-21 19:58:36 -0500[diff] [blame]6#include "imx8mn-u-boot.dtsi"
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]7
8&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]9 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]10};
11
12&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]13 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]14};
15
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]16&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]18};
19
20&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]22};
23
24&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]26};
27
28&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]30};
31
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]32&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]34};
35
36&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]38};
39
40&pinctrl_reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]42};
43
44&pinctrl_uart4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]46};
47
48&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]50};
51
52&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]54};
55
56&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]58};
59
60&uart4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]62};
63
64&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]66};
67
68&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]70};