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git01.mediatek.com / filogic / uboot / cefdc034bbf172d12e1278e478ee28f2f0241d0c / . / arch / arm / dts / imx6ull-phytec-segin-ff-rdk-emmc.dts
blob: 8e2a4c5d7765082ba404a9cbc0000f77ba5da813 [file] [log] [blame]
Parthiban Nallathambideee8c22019-11-04 19:50:07 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2019 PHYTEC Messtechnik GmbH
4 * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
5 */
6
7/dts-v1/;
8#include "imx6ull.dtsi"
9#include "imx6ull-phytec-phycore-som.dtsi"
10#include "imx6ull-phytec-segin.dtsi"
11#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
Marcel Ziswiler64e36c12022-07-21 15:27:30 +0200[diff] [blame]12#include "imx6ull-phytec-segin-peb-av-02.dtsi"
Parthiban Nallathambideee8c22019-11-04 19:50:07 +0100[diff] [blame]13
14/ {
15 model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC";
16 compatible = "phytec,imx6ull-pbacd10-emmc", "phytec,imx6ull-pbacd10",
17 "phytec,imx6ull-pcl063","fsl,imx6ull";
18};
19
20&adc1 {
21 status = "okay";
22};
23
24&can1 {
25 status = "okay";
26};
27
28&tlv320 {
29 status = "okay";
30};
31
32&ecspi3 {
33 status = "okay";
34};
35
36&ethphy1 {
37 status = "okay";
38};
39
40&ethphy2 {
41 status = "okay";
42};
43
44&fec1 {
45 status = "okay";
46};
47
48&fec2 {
49 status = "okay";
50};
51
52&i2c_rtc {
53 status = "okay";
54};
55
56&reg_can1_en {
57 status = "okay";
58};
59
60&reg_sound_1v8 {
61 status = "okay";
62};
63
64&reg_sound_3v3 {
65 status = "okay";
66};
67
68&sai2 {
69 status = "okay";
70};
71
72&sound {
73 status = "okay";
74};
75
76&uart5 {
77 status = "okay";
78};
79
80&usbotg1 {
81 status = "okay";
82};
83
84&usbotg2 {
85 status = "okay";
86};
87
88&usdhc1 {
89 status = "okay";
90};
91
92&usdhc2 {
93 status = "okay";
94};