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git01.mediatek.com / filogic / uboot / cefdc034bbf172d12e1278e478ee28f2f0241d0c / . / arch / arm / dts / imx6ul-14x14-evk-u-boot.dtsi
blob: eaa2a45fedc541b3734c0596d3a69f1b49b36276 [file] [log] [blame]
Ye Li19353b62018-06-27 20:23:16 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
Peng Fanf2e78c82019-08-01 06:02:49 +0000[diff] [blame]6&{/aliases} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]7 bootph-all;
Peng Fanf2e78c82019-08-01 06:02:49 +0000[diff] [blame]8 display0 = &lcdif;
9};
10
Marcel Ziswiler14f3c5a2022-10-22 23:59:32 +0200[diff] [blame]11&soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-all;
Peng Fanf2e78c82019-08-01 06:02:49 +0000[diff] [blame]13};
14
15&aips2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]16 bootph-all;
Peng Fanf2e78c82019-08-01 06:02:49 +0000[diff] [blame]17};
18
19&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-all;
Peng Fanf2e78c82019-08-01 06:02:49 +0000[diff] [blame]21};
22
23&lcdif {
24 display = <&display0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-all;
Peng Fanf2e78c82019-08-01 06:02:49 +0000[diff] [blame]26
27 display0: display@0 {
Anatolij Gustschinbeea8fe2020-02-05 17:49:59 +0100[diff] [blame]28 bits-per-pixel = <24>;
Peng Fanf2e78c82019-08-01 06:02:49 +0000[diff] [blame]29 bus-width = <24>;
30
31 display-timings {
32 native-mode = <&timing0>;
33
34 timing0: timing0 {
35 clock-frequency = <9200000>;
36 hactive = <480>;
37 vactive = <272>;
38 hfront-porch = <8>;
39 hback-porch = <4>;
40 hsync-len = <41>;
41 vback-porch = <2>;
42 vfront-porch = <4>;
43 vsync-len = <10>;
44 hsync-active = <0>;
45 vsync-active = <0>;
46 de-active = <1>;
47 pixelclk-active = <0>;
48 };
49 };
50 };
51};