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git01.mediatek.com / filogic / uboot / cefdc034bbf172d12e1278e478ee28f2f0241d0c / . / arch / arm / dts / fsl-imx8qxp-colibri-u-boot.dtsi
blob: de014c8651e20ece3ebe9a49e1f789873ce4ba25 [file] [log] [blame]
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2019 Toradex AG
4 */
5
Oliver Graute7886cb52022-11-04 16:03:43 +0100[diff] [blame]6#include "imx8qxp-u-boot.dtsi"
7
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]8&{/imx8qx-pm} {
9
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]10 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]11};
12
13&mu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]14 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]15};
16
17&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]19};
20
21&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]23};
24
25&pd_lsio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]27};
28
29&pd_lsio_gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]31};
32
33&pd_lsio_gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]35};
36
37&pd_lsio_gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]39};
40
41&pd_lsio_gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]43};
44
45&pd_lsio_gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]47};
48
49&pd_lsio_gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]51};
52
53&pd_lsio_gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]55};
56
57&pd_lsio_gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]59};
60
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]61&pd_dma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-some-ram;
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]63};
64
65&pd_dma_lpuart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-some-ram;
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]67};
68
69&pd_dma_lpuart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-some-ram;
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]71};
72
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]73&pd_conn {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]75};
76
77&pd_conn_sdch0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]79};
80
81&pd_conn_sdch1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]83};
84
85&pd_conn_sdch2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]87};
88
89&gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]91};
92
93&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]95};
96
97&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]99};
100
101&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]103};
104
105&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]107};
108
109&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]111};
112
113&gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]115};
116
117&gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]119};
120
121&lpuart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]122 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]123};
124
125&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]127};
128
129&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]130 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]131};