blob: 68e9c0bd146158f809ec7cbe9f39325b8e3e9c1a [file] [log] [blame]
Konstantin Porotchkin1232e2e2021-05-11 08:11:24 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018-2021 Marvell International Ltd.
4 */
5/ {
6 /* This should go only into devel boards */
7 compatible = "marvell,cp110";
8 sar {
9 #address-cells = <1>;
10 #size-cells = <0>;
11
12 sar_fields {
13 compatible = "marvell,sample-at-reset";
14 reg = <0x4c 0x4e>;
15 chip_count = <2>;
16 bit_width = <5>;
17 freq {
18 key = "freq";
19 description = "CPU/DDR and PIDI frequencies";
20 start-bit = <0>;
21 bit-length = <4>;
22 option-cnt = <3>;
23 options = "0x0", "CPU/DDR = 0x0: 2000/1200 Mhz, PIDI = 0: 1Ghz",
24 "0x2", "CPU/DDR = 0x6: 2200/1200 Mhz, PIDI = 0: 1Ghz",
25 "0x4", "CPU/DDR = 0xD: 1600/1200 Mhz, PIDI = 0: 1Ghz";
26 default = <0x2>;
27 status = "okay";
28 };
29 boot_mode {
30 key = "boot_mode";
31 description = "Boot mode options";
32 start-bit = <4>;
33 bit-length = <6>;
34 option-cnt = <4>;
35 options = "0xE", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-4bit\t(supported configuration: B)",
36 "0xF", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-8bit\t(supported configuration: B)",
37 "0x2A", "AP_EMMC",
38 "0x32", "CP1_SPI_1 24bits";
39 default = <0x32>;
40 status = "okay";
41 };
42 };
43 };
44};