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git01.mediatek.com / filogic / uboot / cefdc034bbf172d12e1278e478ee28f2f0241d0c / . / arch / arm / dts / ast2500-evb.dts
blob: d481eadfeb0fd40ac43fd65b8d555b3e4c848850 [file] [log] [blame]
maxims@google.com7cb5a002017-01-18 13:44:58 -0800[diff] [blame]1/dts-v1/;
2
3#include "ast2500-u-boot.dtsi"
4
5/ {
6 memory {
7 device_type = "memory";
8 reg = <0x80000000 0x20000000>;
9 };
10
11 chosen {
12 stdout-path = &uart5;
13 };
Cédric Le Goater117bd462018-10-29 07:06:40 +0100[diff] [blame]14
15 aliases {
16 ethernet0 = &mac0;
17 ethernet1 = &mac1;
18 };
maxims@google.com7cb5a002017-01-18 13:44:58 -0800[diff] [blame]19};
20
21&uart5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-all;
maxims@google.com7cb5a002017-01-18 13:44:58 -0800[diff] [blame]23 status = "okay";
24};
25
26&sdrammc {
27 clock-frequency = <400000000>;
28};
maxims@google.comed365e32017-04-17 12:00:25 -0700[diff] [blame]29
30&wdt1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-all;
maxims@google.comed365e32017-04-17 12:00:25 -0700[diff] [blame]32 status = "okay";
33};
34
35&wdt2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-all;
maxims@google.comed365e32017-04-17 12:00:25 -0700[diff] [blame]37 status = "okay";
38};
39
40&wdt3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-all;
maxims@google.comed365e32017-04-17 12:00:25 -0700[diff] [blame]42 status = "okay";
Cédric Le Goater117bd462018-10-29 07:06:40 +0100[diff] [blame]43};
44
45&mac0 {
46 status = "okay";
47
48 phy-mode = "rgmii";
49
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_mac1link_default &pinctrl_mdio1_default>;
52};
53
54&mac1 {
55 status = "okay";
56
57 phy-mode = "rgmii";
58
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
maxims@google.comed365e32017-04-17 12:00:25 -0700[diff] [blame]61};
Eddie James6bd7aeb2019-08-15 14:29:40 -0500[diff] [blame]62
Joel Stanley333f27c2022-06-23 18:35:29 +0930[diff] [blame]63&sdmmc {
64 status = "okay";
65};
66
Eddie James6bd7aeb2019-08-15 14:29:40 -0500[diff] [blame]67&sdhci0 {
68 status = "okay";
69
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_sd1_default>;
72};
73
74&sdhci1 {
75 status = "okay";
76
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_sd2_default>;
79};
Joel Stanley2053fdd2022-06-23 14:40:35 +0930[diff] [blame]80
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]81&fmc {
82 status = "okay";
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_fwspics1_default>;
85
86 flash@0 {
87 status = "okay";
88 spi-max-frequency = <50000000>;
89 spi-tx-bus-width = <2>;
90 spi-rx-bus-width = <2>;
91 };
92
93 flash@1 {
94 status = "okay";
95 spi-max-frequency = <50000000>;
96 spi-tx-bus-width = <2>;
97 spi-rx-bus-width = <2>;
98 };
99};
100
101&spi1 {
102 status = "okay";
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_spi1cs1_default>;
105
106 flash@0 {
107 status = "okay";
108 spi-max-frequency = <50000000>;
109 spi-tx-bus-width = <2>;
110 spi-rx-bus-width = <2>;
111 };
112};
113
Joel Stanley2053fdd2022-06-23 14:40:35 +0930[diff] [blame]114&i2c3 {
115 status = "okay";
116
117 eeprom@50 {
118 compatible = "atmel,24c08";
119 reg = <0x50>;
120 pagesize = <16>;
121 };
122};
123
124&i2c7 {
125 status = "okay";
126
127 lm75@4d {
128 compatible = "national,lm75";
129 reg = <0x4d>;
130 };
131};