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git01.mediatek.com / filogic / uboot / cede5d8996eb427ed56013bf922b2cc04bef0f2e / . / include / asm-sparc / winmacro.h
blob: 66fc639a7e8a5039f23b07b6f307279e2a17c145 [file] [log] [blame]
Daniel Hellstrom9d7c6b22008-03-28 09:47:00 +0100[diff] [blame]1/*
2 * Added to U-boot,
3 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
4 * Copyright (C) 2007
5 *
6 * LEON2/3 LIBIO low-level routines
7 * Written by Jiri Gaisler.
8 * Copyright (C) 2004 Gaisler Research AB
9
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23
24*/
25
26#ifndef __SPARC_WINMACRO_H__
27#define __SPARC_WINMACRO_H__
28
29#include <asm/asmmacro.h>
30#include <asm/stack.h>
31
32/* Store the register window onto the 8-byte aligned area starting
33 * at %reg. It might be %sp, it might not, we don't care.
34 */
35#define RW_STORE(reg) \
36 std %l0, [%reg + RW_L0]; \
37 std %l2, [%reg + RW_L2]; \
38 std %l4, [%reg + RW_L4]; \
39 std %l6, [%reg + RW_L6]; \
40 std %i0, [%reg + RW_I0]; \
41 std %i2, [%reg + RW_I2]; \
42 std %i4, [%reg + RW_I4]; \
43 std %i6, [%reg + RW_I6];
44
45/* Load a register window from the area beginning at %reg. */
46#define RW_LOAD(reg) \
47 ldd [%reg + RW_L0], %l0; \
48 ldd [%reg + RW_L2], %l2; \
49 ldd [%reg + RW_L4], %l4; \
50 ldd [%reg + RW_L6], %l6; \
51 ldd [%reg + RW_I0], %i0; \
52 ldd [%reg + RW_I2], %i2; \
53 ldd [%reg + RW_I4], %i4; \
54 ldd [%reg + RW_I6], %i6;
55
56/* Loading and storing struct pt_reg trap frames. */
57#define PT_LOAD_INS(base_reg) \
58 ldd [%base_reg + SF_REGS_SZ + PT_I0], %i0; \
59 ldd [%base_reg + SF_REGS_SZ + PT_I2], %i2; \
60 ldd [%base_reg + SF_REGS_SZ + PT_I4], %i4; \
61 ldd [%base_reg + SF_REGS_SZ + PT_I6], %i6;
62
63#define PT_LOAD_GLOBALS(base_reg) \
64 ld [%base_reg + SF_REGS_SZ + PT_G1], %g1; \
65 ldd [%base_reg + SF_REGS_SZ + PT_G2], %g2; \
66 ldd [%base_reg + SF_REGS_SZ + PT_G4], %g4; \
67 ldd [%base_reg + SF_REGS_SZ + PT_G6], %g6;
68
69#define PT_LOAD_YREG(base_reg, scratch) \
70 ld [%base_reg + SF_REGS_SZ + PT_Y], %scratch; \
71 wr %scratch, 0x0, %y;
72
73#define PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
74 ld [%base_reg + SF_REGS_SZ + PT_PSR], %pt_psr; \
75 ld [%base_reg + SF_REGS_SZ + PT_PC], %pt_pc; \
76 ld [%base_reg + SF_REGS_SZ + PT_NPC], %pt_npc;
77
78#define PT_LOAD_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \
79 PT_LOAD_YREG(base_reg, scratch) \
80 PT_LOAD_INS(base_reg) \
81 PT_LOAD_GLOBALS(base_reg) \
82 PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc)
83
84#define PT_STORE_INS(base_reg) \
85 std %i0, [%base_reg + SF_REGS_SZ + PT_I0]; \
86 std %i2, [%base_reg + SF_REGS_SZ + PT_I2]; \
87 std %i4, [%base_reg + SF_REGS_SZ + PT_I4]; \
88 std %i6, [%base_reg + SF_REGS_SZ + PT_I6];
89
90#define PT_STORE_GLOBALS(base_reg) \
91 st %g1, [%base_reg + SF_REGS_SZ + PT_G1]; \
92 std %g2, [%base_reg + SF_REGS_SZ + PT_G2]; \
93 std %g4, [%base_reg + SF_REGS_SZ + PT_G4]; \
94 std %g6, [%base_reg + SF_REGS_SZ + PT_G6];
95
96#define PT_STORE_YREG(base_reg, scratch) \
97 rd %y, %scratch; \
98 st %scratch, [%base_reg + SF_REGS_SZ + PT_Y];
99
100#define PT_STORE_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
101 st %pt_psr, [%base_reg + SF_REGS_SZ + PT_PSR]; \
102 st %pt_pc, [%base_reg + SF_REGS_SZ + PT_PC]; \
103 st %pt_npc, [%base_reg + SF_REGS_SZ + PT_NPC];
104
105#define PT_STORE_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \
106 PT_STORE_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \
107 PT_STORE_GLOBALS(base_reg) \
108 PT_STORE_YREG(base_reg, g_scratch) \
109 PT_STORE_INS(base_reg)
110
111/* Store the fpu register window*/
112#define FW_STORE(reg) \
113 std %f0, [reg + FW_F0]; \
114 std %f2, [reg + FW_F2]; \
115 std %f4, [reg + FW_F4]; \
116 std %f6, [reg + FW_F6]; \
117 std %f8, [reg + FW_F8]; \
118 std %f10, [reg + FW_F10]; \
119 std %f12, [reg + FW_F12]; \
120 std %f14, [reg + FW_F14]; \
121 std %f16, [reg + FW_F16]; \
122 std %f18, [reg + FW_F18]; \
123 std %f20, [reg + FW_F20]; \
124 std %f22, [reg + FW_F22]; \
125 std %f24, [reg + FW_F24]; \
126 std %f26, [reg + FW_F26]; \
127 std %f28, [reg + FW_F28]; \
128 std %f30, [reg + FW_F30]; \
129 st %fsr, [reg + FW_FSR];
130
131/* Load a fpu register window from the area beginning at reg. */
132#define FW_LOAD(reg) \
133 ldd [reg + FW_F0], %f0; \
134 ldd [reg + FW_F2], %f2; \
135 ldd [reg + FW_F4], %f4; \
136 ldd [reg + FW_F6], %f6; \
137 ldd [reg + FW_F8], %f8; \
138 ldd [reg + FW_F10], %f10; \
139 ldd [reg + FW_F12], %f12; \
140 ldd [reg + FW_F14], %f14; \
141 ldd [reg + FW_F16], %f16; \
142 ldd [reg + FW_F18], %f18; \
143 ldd [reg + FW_F20], %f20; \
144 ldd [reg + FW_F22], %f22; \
145 ldd [reg + FW_F24], %f24; \
146 ldd [reg + FW_F26], %f26; \
147 ldd [reg + FW_F28], %f28; \
148 ldd [reg + FW_F30], %f30; \
149 ld [reg + FW_FSR], %fsr;
150
151#endif