| Chanho Park | a23ab3d | 2023-10-31 17:55:59 +0900 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2023 StarFive Technology Co., Ltd. |
| 4 | * Author: yanhong <yanhong.wang@starfivetech.com> |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef _GPIO_STARFIVE_H_ |
| 9 | #define _GPIO_STARFIVE_H_ |
| 10 | |
| 11 | #include <asm/arch/regs.h> |
| 12 | |
| 13 | #define GPIO_NUM_SHIFT 2 /*one dword include 4 gpios*/ |
| 14 | #define GPIO_BYTE_SHIFT 3 |
| 15 | |
| 16 | #define GPIO_INDEX_MASK 0x3 |
| 17 | |
| 18 | #define GPIO_DOEN_MASK 0x3f |
| 19 | #define GPIO_DOUT_MASK 0x7f |
| 20 | #define GPIO_DIN_MASK 0x7f |
| 21 | #define GPIO_DS_MASK 0x06 |
| 22 | #define GPIO_DS_SHIFT 1 |
| 23 | #define GPIO_SLEW_MASK BIT(5) |
| 24 | #define GPIO_SLEW_SHIFT 5 |
| 25 | #define GPIO_PULL_MASK 0x18 |
| 26 | #define GPIO_PULL_SHIFT 3 |
| 27 | #define GPIO_PULL_UP 1 |
| 28 | #define GPIO_PULL_DOWN 2 |
| 29 | |
| 30 | #define NR_GPIOS 64 |
| 31 | |
| 32 | #define GPIO_OFFSET(gpio) \ |
| 33 | (((gpio) >> GPIO_NUM_SHIFT) << GPIO_NUM_SHIFT) |
| 34 | |
| 35 | #define GPIO_SHIFT(gpio) \ |
| 36 | (((gpio) & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT) |
| 37 | |
| 38 | enum gpio_state { |
| 39 | LOW, |
| 40 | HIGH |
| 41 | }; |
| 42 | |
| 43 | #define GPIO_DOEN 0x0 |
| 44 | #define GPIO_DOUT 0x40 |
| 45 | #define GPIO_DIN 0x80 |
| 46 | #define GPIO_EN 0xdc |
| 47 | #define GPIO_LOW_IE 0x100 |
| 48 | #define GPIO_HIGH_IE 0x104 |
| 49 | #define GPIO_CONFIG 0x120 |
| 50 | |
| 51 | #define SYS_IOMUX_DOEN(gpio, oen) \ |
| 52 | clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_OFFSET(gpio), \ |
| 53 | GPIO_DOEN_MASK << GPIO_SHIFT(gpio), \ |
| 54 | (oen) << GPIO_SHIFT(gpio)) |
| 55 | |
| 56 | #define SYS_IOMUX_DOUT(gpio, gpo) \ |
| 57 | clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DOUT + GPIO_OFFSET(gpio), \ |
| 58 | GPIO_DOUT_MASK << GPIO_SHIFT(gpio), \ |
| 59 | ((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio)) |
| 60 | |
| 61 | #define SYS_IOMUX_DIN(gpio, gpi)\ |
| 62 | clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \ |
| 63 | GPIO_DIN_MASK << GPIO_SHIFT(gpi), \ |
| 64 | ((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi)) |
| 65 | |
| 66 | #define SYS_IOMUX_SET_DS(gpio, ds) \ |
| 67 | clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \ |
| 68 | GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT) |
| 69 | |
| 70 | #define SYS_IOMUX_SET_SLEW(gpio, slew) \ |
| 71 | clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \ |
| 72 | GPIO_SLEW_MASK, (slew) << GPIO_SLEW_SHIFT) |
| 73 | |
| 74 | #define SYS_IOMUX_SET_PULL(gpio, pull) \ |
| 75 | clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \ |
| 76 | GPIO_PULL_MASK, (pull) << GPIO_PULL_SHIFT) |
| 77 | |
| 78 | #define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) \ |
| 79 | do { \ |
| 80 | SYS_IOMUX_DOEN(gpio, oen); \ |
| 81 | SYS_IOMUX_DOUT(gpio, gpo); \ |
| 82 | SYS_IOMUX_DIN(gpio, gpi); \ |
| 83 | } while (0) |
| 84 | |
| 85 | #endif /* _GPIO_STARFIVE_H_ */ |