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git01.mediatek.com / filogic / uboot / ced7f0723f292590679164f899b2a1b2f430d1a8 / . / drivers / pinctrl / rockchip / pinctrl-rk3568.c
blob: 935aed9efc62dec1609e19674937da0b73af2849 [file] [log] [blame]
Jagan Teki7fc80642023-02-17 17:28:43 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <dm/pinctrl.h>
9#include <regmap.h>
10#include <syscon.h>
11#include <dt-bindings/pinctrl/rockchip.h>
12
13#include "pinctrl-rockchip.h"
14
15static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
16 MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */
17 MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */
18 MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */
19 MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */
20 MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */
21 MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */
22 MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */
23 MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */
24 MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */
25 MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */
26 MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */
27 MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */
28 MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */
29 MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */
30 MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */
31 MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */
32 MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */
33 MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */
34 MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */
35 MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */
36 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */
37 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */
38 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */
39 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */
40 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */
41 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */
42 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */
43 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */
44 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
45 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
46 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
47 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
48 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
49 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
50 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
51 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
52 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
53 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
54 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
55 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
56 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
57 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
58 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
59 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
60 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */
61 MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */
62 MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */
63 MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */
64 MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */
65 MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */
66 MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */
67 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */
68 MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */
69 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */
70 MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */
71 MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
72 MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */
73 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */
74 MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */
75 MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */
76 MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */
77 MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */
78 MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */
79 MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */
80 MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */
81 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */
82 MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */
83 MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */
84 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
85 MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */
86 MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */
87 MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */
88 MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */
89 MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */
90 MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */
91 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */
92 MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */
93 MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */
94 MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */
95 MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */
96 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */
97 MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */
98 MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */
99 MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */
100 MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */
101 MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */
102 MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */
103 MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */
104 MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */
105 MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */
106 MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */
107 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */
108};
109
110static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
111{
112 struct rockchip_pinctrl_priv *priv = bank->priv;
113 int iomux_num = (pin / 8);
114 struct regmap *regmap;
115 int reg, ret, mask;
116 u8 bit;
117 u32 data;
118
119 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
120
121 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
122 regmap = priv->regmap_pmu;
123 else
124 regmap = priv->regmap_base;
125
126 reg = bank->iomux[iomux_num].offset;
127 if ((pin % 8) >= 4)
128 reg += 0x4;
129 bit = (pin % 4) * 4;
130 mask = 0xf;
131
132 data = (mask << (bit + 16));
133 data |= (mux & mask) << bit;
134 ret = regmap_write(regmap, reg, data);
135
136 return ret;
137}
138
139#define RK3568_PULL_PMU_OFFSET 0x20
140#define RK3568_PULL_GRF_OFFSET 0x80
141#define RK3568_PULL_BITS_PER_PIN 2
142#define RK3568_PULL_PINS_PER_REG 8
143#define RK3568_PULL_BANK_STRIDE 0x10
144
145static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
146 int pin_num, struct regmap **regmap,
147 int *reg, u8 *bit)
148{
149 struct rockchip_pinctrl_priv *info = bank->priv;
150
151 if (bank->bank_num == 0) {
152 *regmap = info->regmap_pmu;
153 *reg = RK3568_PULL_PMU_OFFSET;
154 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
155 } else {
156 *regmap = info->regmap_base;
157 *reg = RK3568_PULL_GRF_OFFSET;
158 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
159 }
160
161 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
162 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
163 *bit *= RK3568_PULL_BITS_PER_PIN;
164}
165
166#define RK3568_DRV_PMU_OFFSET 0x70
167#define RK3568_DRV_GRF_OFFSET 0x200
168#define RK3568_DRV_BITS_PER_PIN 8
169#define RK3568_DRV_PINS_PER_REG 2
170#define RK3568_DRV_BANK_STRIDE 0x40
171
172static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
173 int pin_num, struct regmap **regmap,
174 int *reg, u8 *bit)
175{
176 struct rockchip_pinctrl_priv *info = bank->priv;
177
178 /* The first 32 pins of the first bank are located in PMU */
179 if (bank->bank_num == 0) {
180 *regmap = info->regmap_pmu;
181 *reg = RK3568_DRV_PMU_OFFSET;
182 } else {
183 *regmap = info->regmap_base;
184 *reg = RK3568_DRV_GRF_OFFSET;
185 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
186 }
187
188 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
189 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
190 *bit *= RK3568_DRV_BITS_PER_PIN;
191}
192
193#define RK3568_SCHMITT_BITS_PER_PIN 2
194#define RK3568_SCHMITT_PINS_PER_REG 8
195#define RK3568_SCHMITT_BANK_STRIDE 0x10
196#define RK3568_SCHMITT_GRF_OFFSET 0xc0
197#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
198
199static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
200 int pin_num, struct regmap **regmap,
201 int *reg, u8 *bit)
202{
203 struct rockchip_pinctrl_priv *info = bank->priv;
204
205 if (bank->bank_num == 0) {
206 *regmap = info->regmap_pmu;
207 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
208 } else {
209 *regmap = info->regmap_base;
210 *reg = RK3568_SCHMITT_GRF_OFFSET;
211 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
212 }
213
214 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
215 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
216 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
217
218 return 0;
219}
220
221static int rk3568_set_pull(struct rockchip_pin_bank *bank,
222 int pin_num, int pull)
223{
224 struct regmap *regmap;
225 int reg, ret;
226 u8 bit, type;
227 u32 data;
228
229 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
230 return -ENOTSUPP;
231
232 rk3568_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
233 type = bank->pull_type[pin_num / 8];
234 ret = rockchip_translate_pull_value(type, pull);
235 if (ret < 0) {
236 debug("unsupported pull setting %d\n", pull);
237 return ret;
238 }
239
240 /* enable the write to the equivalent lower bits */
241 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
242
243 data |= (ret << bit);
244 ret = regmap_write(regmap, reg, data);
245
246 return ret;
247}
248
249static int rk3568_set_drive(struct rockchip_pin_bank *bank,
250 int pin_num, int strength)
251{
252 struct regmap *regmap;
253 int reg;
254 u32 data;
255 u8 bit;
256 int drv = (1 << (strength + 1)) - 1;
257 int ret = 0;
258
259 rk3568_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
260
261 /* enable the write to the equivalent lower bits */
262 data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
263 data |= (drv << bit);
264
265 ret = regmap_write(regmap, reg, data);
266 if (ret)
267 return ret;
268
269 if (bank->bank_num == 1 && pin_num == 21)
270 reg = 0x0840;
271 else if (bank->bank_num == 2 && pin_num == 2)
272 reg = 0x0844;
273 else if (bank->bank_num == 2 && pin_num == 8)
274 reg = 0x0848;
275 else if (bank->bank_num == 3 && pin_num == 0)
276 reg = 0x084c;
277 else if (bank->bank_num == 3 && pin_num == 6)
278 reg = 0x0850;
279 else if (bank->bank_num == 4 && pin_num == 0)
280 reg = 0x0854;
281 else
282 return 0;
283
284 data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
285 data |= drv;
286
287 return regmap_write(regmap, reg, data);
288}
289
290static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
291 int pin_num, int enable)
292{
293 struct regmap *regmap;
294 int reg;
295 u32 data;
296 u8 bit;
297
298 rk3568_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
299
300 /* enable the write to the equivalent lower bits */
301 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
302 data |= (enable << bit);
303
304 return regmap_write(regmap, reg, data);
305}
306
307static struct rockchip_pin_bank rk3568_pin_banks[] = {
308 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
309 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
310 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
311 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
312 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
313 IOMUX_WIDTH_4BIT,
314 IOMUX_WIDTH_4BIT,
315 IOMUX_WIDTH_4BIT),
316 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
317 IOMUX_WIDTH_4BIT,
318 IOMUX_WIDTH_4BIT,
319 IOMUX_WIDTH_4BIT),
320 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
321 IOMUX_WIDTH_4BIT,
322 IOMUX_WIDTH_4BIT,
323 IOMUX_WIDTH_4BIT),
324 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
325 IOMUX_WIDTH_4BIT,
326 IOMUX_WIDTH_4BIT,
327 IOMUX_WIDTH_4BIT),
328};
329
330static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
331 .pin_banks = rk3568_pin_banks,
332 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
333 .nr_pins = 160,
334 .grf_mux_offset = 0x0,
335 .pmu_mux_offset = 0x0,
336 .iomux_routes = rk3568_mux_route_data,
337 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
338 .set_mux = rk3568_set_mux,
339 .set_pull = rk3568_set_pull,
340 .set_drive = rk3568_set_drive,
341 .set_schmitt = rk3568_set_schmitt,
342};
343
344static const struct udevice_id rk3568_pinctrl_ids[] = {
345 {
346 .compatible = "rockchip,rk3568-pinctrl",
347 .data = (ulong)&rk3568_pin_ctrl
348 },
349 { }
350};
351
352U_BOOT_DRIVER(pinctrl_rk3568) = {
353 .name = "rockchip_rk3568_pinctrl",
354 .id = UCLASS_PINCTRL,
355 .of_match = rk3568_pinctrl_ids,
356 .priv_auto = sizeof(struct rockchip_pinctrl_priv),
357 .ops = &rockchip_pinctrl_ops,
358#if CONFIG_IS_ENABLED(OF_REAL)
359 .bind = dm_scan_fdt_dev,
360#endif
361 .probe = rockchip_pinctrl_probe,
362};