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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Shengzhou Liu49912402014-11-24 17:11:56 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Shengzhou Liu49912402014-11-24 17:11:56 +08004 */
5
6#include <common.h>
7#include <asm/fsl_law.h>
8#include <asm/mmu.h>
9
10struct law_entry law_table[] = {
Masahiro Yamada8cea9b52017-02-11 22:43:54 +090011#ifdef CONFIG_MTD_NOR_FLASH
Tom Rini6a5dccc2022-11-16 13:10:41 -050012 SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
Shengzhou Liu49912402014-11-24 17:11:56 +080013#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -050014#ifdef CFG_SYS_BMAN_MEM_PHYS
15 SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
Shengzhou Liu49912402014-11-24 17:11:56 +080016#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -050017#ifdef CFG_SYS_QMAN_MEM_PHYS
18 SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
Shengzhou Liu49912402014-11-24 17:11:56 +080019#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -050020#ifdef CFG_SYS_CPLD_BASE_PHYS
21 SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
Shengzhou Liu49912402014-11-24 17:11:56 +080022#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -050023#ifdef CFG_SYS_DCSRBAR_PHYS
24 SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
Shengzhou Liu49912402014-11-24 17:11:56 +080025#endif
Tom Rinib4213492022-11-12 17:36:51 -050026#ifdef CFG_SYS_NAND_BASE_PHYS
27 SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
Shengzhou Liu49912402014-11-24 17:11:56 +080028#endif
29};
30
31int num_law_entries = ARRAY_SIZE(law_table);