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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Gregory CLEMENTa2490a22017-05-09 13:36:21 +02002/*
3 * U-Boot Marvell 37xx SoC pinctrl driver
4 *
5 * Copyright (C) 2017 Stefan Roese <sr@denx.de>
6 *
7 * This driver is based on the Linux driver version, which is:
8 * Copyright (C) 2017 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 *
11 * Additionally parts are derived from the Meson U-Boot pinctrl driver,
12 * which is:
13 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
14 * Based on code from Linux kernel:
15 * Copyright (C) 2016 Endless Mobile, Inc.
Gregory CLEMENTa2490a22017-05-09 13:36:21 +020016 * https://spdx.org/licenses
17 */
18
19#include <common.h>
20#include <config.h>
21#include <dm.h>
Simon Glass9bc15642020-02-03 07:36:16 -070022#include <malloc.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060023#include <asm/global_data.h>
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +020024#include <dm/device-internal.h>
Simon Glass9bc15642020-02-03 07:36:16 -070025#include <dm/device_compat.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070026#include <dm/devres.h>
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +020027#include <dm/lists.h>
Gregory CLEMENTa2490a22017-05-09 13:36:21 +020028#include <dm/pinctrl.h>
29#include <dm/root.h>
30#include <errno.h>
31#include <fdtdec.h>
32#include <regmap.h>
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +020033#include <asm/gpio.h>
Gregory CLEMENTa2490a22017-05-09 13:36:21 +020034#include <asm/system.h>
35#include <asm/io.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060036#include <linux/bitops.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060037#include <linux/libfdt.h>
Gregory CLEMENTa2490a22017-05-09 13:36:21 +020038
39DECLARE_GLOBAL_DATA_PTR;
40
41#define OUTPUT_EN 0x0
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +020042#define INPUT_VAL 0x10
43#define OUTPUT_VAL 0x18
Gregory CLEMENTa2490a22017-05-09 13:36:21 +020044#define OUTPUT_CTL 0x20
45#define SELECTION 0x30
46
47#define IRQ_EN 0x0
48#define IRQ_POL 0x08
49#define IRQ_STATUS 0x10
50#define IRQ_WKUP 0x18
51
Ken Mab28aedb2018-03-26 15:56:01 +080052#define NB_FUNCS 3
Gregory CLEMENTa2490a22017-05-09 13:36:21 +020053#define GPIO_PER_REG 32
54
55/**
56 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
57 * The pins of a pinmux groups are composed of one or two groups of contiguous
58 * pins.
59 * @name: Name of the pin group, used to lookup the group.
60 * @start_pins: Index of the first pin of the main range of pins belonging to
61 * the group
62 * @npins: Number of pins included in the first range
63 * @reg_mask: Bit mask matching the group in the selection register
64 * @extra_pins: Index of the first pin of the optional second range of pins
65 * belonging to the group
66 * @npins: Number of pins included in the second optional range
67 * @funcs: A list of pinmux functions that can be selected for this group.
Gregory CLEMENTa2490a22017-05-09 13:36:21 +020068 */
69struct armada_37xx_pin_group {
70 const char *name;
71 unsigned int start_pin;
72 unsigned int npins;
73 u32 reg_mask;
74 u32 val[NB_FUNCS];
75 unsigned int extra_pin;
76 unsigned int extra_npins;
77 const char *funcs[NB_FUNCS];
Gregory CLEMENTa2490a22017-05-09 13:36:21 +020078};
79
80struct armada_37xx_pin_data {
81 u8 nr_pins;
82 char *name;
83 struct armada_37xx_pin_group *groups;
84 int ngroups;
85};
86
87struct armada_37xx_pmx_func {
88 const char *name;
89 const char **groups;
90 unsigned int ngroups;
91};
92
93struct armada_37xx_pinctrl {
94 void __iomem *base;
95 const struct armada_37xx_pin_data *data;
96 struct udevice *dev;
97 struct pinctrl_dev *pctl_dev;
Gregory CLEMENTa2490a22017-05-09 13:36:21 +020098 struct armada_37xx_pmx_func *funcs;
99 unsigned int nfuncs;
100};
101
Pali Rohár0738d9d2022-07-25 14:09:01 +0200102#define PIN_GRP_GPIO_0(_name, _start, _nr) \
103 { \
104 .name = _name, \
105 .start_pin = _start, \
106 .npins = _nr, \
107 .reg_mask = 0, \
108 .val = {0}, \
109 .funcs = {"gpio"} \
110 }
111
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200112#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
113 { \
114 .name = _name, \
115 .start_pin = _start, \
116 .npins = _nr, \
117 .reg_mask = _mask, \
118 .val = {0, _mask}, \
119 .funcs = {_func1, "gpio"} \
120 }
121
122#define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
123 { \
124 .name = _name, \
125 .start_pin = _start, \
126 .npins = _nr, \
127 .reg_mask = _mask, \
128 .val = {_val1, _val2}, \
129 .funcs = {_func1, "gpio"} \
130 }
131
Ken Mab28aedb2018-03-26 15:56:01 +0800132#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
133 { \
134 .name = _name, \
135 .start_pin = _start, \
136 .npins = _nr, \
137 .reg_mask = _mask, \
138 .val = {_v1, _v2, _v3}, \
139 .funcs = {_f1, _f2, "gpio"} \
140 }
141
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200142#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
143 _f1, _f2) \
144 { \
145 .name = _name, \
146 .start_pin = _start, \
147 .npins = _nr, \
148 .reg_mask = _mask, \
149 .val = {_v1, _v2}, \
150 .extra_pin = _start2, \
151 .extra_npins = _nr2, \
152 .funcs = {_f1, _f2} \
153 }
154
155static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
156 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
157 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
158 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
Marek Behún9eaf20b2021-07-23 19:57:11 +0200159 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
160 "pwm", "led"),
Marek Behún54021602022-02-28 15:59:37 +0100161 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
Marek Behún9eaf20b2021-07-23 19:57:11 +0200162 "pwm", "led"),
Marek Behún54021602022-02-28 15:59:37 +0100163 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
Marek Behún9eaf20b2021-07-23 19:57:11 +0200164 "pwm", "led"),
Marek Behún54021602022-02-28 15:59:37 +0100165 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
Marek Behún9eaf20b2021-07-23 19:57:11 +0200166 "pwm", "led"),
Ken Ma3cdd35b2018-03-26 15:56:03 +0800167 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
168 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
Pali Rohár0738d9d2022-07-25 14:09:01 +0200169 PIN_GRP_GPIO_0("gpio1_5", 5, 1),
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200170 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
171 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
172 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
173 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
174 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
175 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
176 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
177 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
Ken Maa12d6372017-06-22 17:13:35 +0800178 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
179 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
180 18, 2, "gpio", "uart"),
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200181};
182
183static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
184 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
185 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
Pali Rohár0738d9d2022-07-25 14:09:01 +0200186 PIN_GRP_GPIO_0("gpio2_2", 2, 1),
Ken Ma3cdd35b2018-03-26 15:56:03 +0800187 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
188 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
189 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
Pali Rohár0738d9d2022-07-25 14:09:01 +0200190 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
191 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
192 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
Pali Rohár3a8dccb2022-08-04 12:41:54 +0200193 PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"),
194 PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12),
195 "ptp", "mii"),
196 PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13),
197 "ptp", "mii"),
Ken Mab28aedb2018-03-26 15:56:01 +0800198 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
199 "mii", "mii_err"),
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200200};
201
Pali Rohár1497f2e2022-07-25 14:09:00 +0200202static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200203 .nr_pins = 36,
204 .name = "GPIO1",
205 .groups = armada_37xx_nb_groups,
206 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
207};
208
Pali Rohár1497f2e2022-07-25 14:09:00 +0200209static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
Ken Maa1d81602018-03-26 15:55:59 +0800210 .nr_pins = 30,
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200211 .name = "GPIO2",
212 .groups = armada_37xx_sb_groups,
213 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
214};
215
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200216static inline void armada_37xx_update_reg(unsigned int *reg,
Ken Maf72c5292018-03-26 15:56:02 +0800217 unsigned int *offset)
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200218{
219 /* We never have more than 2 registers */
Ken Maf72c5292018-03-26 15:56:02 +0800220 if (*offset >= GPIO_PER_REG) {
221 *offset -= GPIO_PER_REG;
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200222 *reg += sizeof(u32);
223 }
224}
225
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200226static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
227 const char *func)
228{
229 int f;
230
Ken Mab28aedb2018-03-26 15:56:01 +0800231 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200232 if (!strcmp(grp->funcs[f], func))
233 return f;
234
235 return -ENOTSUPP;
236}
237
238static int armada_37xx_pmx_get_groups_count(struct udevice *dev)
239{
240 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
241
Pali Rohár579b5d62022-07-25 14:08:59 +0200242 return info->data->ngroups;
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200243}
244
245static const char *armada_37xx_pmx_dummy_name = "_dummy";
246
247static const char *armada_37xx_pmx_get_group_name(struct udevice *dev,
248 unsigned selector)
249{
250 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
251
Pali Rohár579b5d62022-07-25 14:08:59 +0200252 if (!info->data->groups[selector].name)
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200253 return armada_37xx_pmx_dummy_name;
254
Pali Rohár579b5d62022-07-25 14:08:59 +0200255 return info->data->groups[selector].name;
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200256}
257
258static int armada_37xx_pmx_get_funcs_count(struct udevice *dev)
259{
260 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
261
262 return info->nfuncs;
263}
264
265static const char *armada_37xx_pmx_get_func_name(struct udevice *dev,
266 unsigned selector)
267{
268 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
269
270 return info->funcs[selector].name;
271}
272
273static int armada_37xx_pmx_set_by_name(struct udevice *dev,
274 const char *name,
Pali Rohár9eaab3b2022-07-25 14:09:02 +0200275 struct armada_37xx_pin_group *grp,
276 bool warn_on_change)
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200277{
278 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
279 unsigned int reg = SELECTION;
280 unsigned int mask = grp->reg_mask;
Pali Rohár9eaab3b2022-07-25 14:09:02 +0200281 int func, val, old_func;
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200282
283 dev_dbg(info->dev, "enable function %s group %s\n",
284 name, grp->name);
285
286 func = armada_37xx_get_func_reg(grp, name);
287
288 if (func < 0)
289 return func;
290
291 val = grp->val[func];
292
Pali Rohár9eaab3b2022-07-25 14:09:02 +0200293 if (warn_on_change && val != (readl(info->base + reg) & mask)) {
294 for (old_func = 0; (old_func < NB_FUNCS) && grp->funcs[old_func]; old_func++) {
295 if (grp->val[old_func] == val)
296 break;
297 }
298 dev_warn(info->dev, "Warning: Changing MPPs %u-%u function from %s to %s...\n",
299 grp->start_pin, grp->start_pin + grp->npins - 1,
300 ((old_func < NB_FUNCS && grp->funcs[old_func]) ?
301 grp->funcs[old_func] : "unknown"),
302 name);
303 }
304
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200305 clrsetbits_le32(info->base + reg, mask, val);
306
307 return 0;
308}
309
310static int armada_37xx_pmx_group_set(struct udevice *dev,
311 unsigned group_selector,
312 unsigned func_selector)
313{
314 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
Pali Rohár579b5d62022-07-25 14:08:59 +0200315 struct armada_37xx_pin_group *grp = &info->data->groups[group_selector];
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200316 const char *name = info->funcs[func_selector].name;
317
Pali Rohár9eaab3b2022-07-25 14:09:02 +0200318 return armada_37xx_pmx_set_by_name(dev, name, grp, false);
319}
320
321static int armada_37xx_pmx_gpio_request_enable(struct udevice *dev, unsigned int selector)
322{
323 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
324 int ret = -ENOTSUPP;
325 int n;
326
327 /* Find all groups where is requested selector pin and set each group to gpio function */
328 for (n = 0; n < info->data->ngroups; n++) {
329 struct armada_37xx_pin_group *grp = &info->data->groups[n];
330
331 if ((selector >= grp->start_pin && selector < grp->start_pin + grp->npins) ||
332 (selector >= grp->extra_pin && selector < grp->extra_pin + grp->extra_npins)) {
333 ret = armada_37xx_pmx_set_by_name(dev, "gpio", grp, true);
334 if (ret)
335 return ret;
336 }
337 }
338
339 return ret;
340}
341
342static int armada_37xx_pmx_gpio_disable_free(struct udevice *dev, unsigned int selector)
343{
344 /* nothing to do */
345 return 0;
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200346}
347
Pali Rohárf6f0c092022-07-25 14:09:03 +0200348static int armada_37xx_pmx_get_pins_count(struct udevice *dev)
349{
350 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
351
352 return info->data->nr_pins;
353}
354
355static const char *armada_37xx_pmx_get_pin_name(struct udevice *dev, unsigned int selector)
356{
357 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
358 static char buf[sizeof("MPPx_XX")];
359
360 sprintf(buf, "MPP%c_%u", info->data->name[4], selector);
361 return buf;
362}
363
364static int armada_37xx_pmx_get_pin_muxing(struct udevice *dev, unsigned int selector,
365 char *buf, int size)
366{
367 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
368 int n;
369
370 /*
371 * First check if selected pin is in some extra pin group.
372 * Function in extra pin group is active only when it is not gpio.
373 */
374 for (n = 0; n < info->data->ngroups; n++) {
375 struct armada_37xx_pin_group *grp = &info->data->groups[n];
376
377 if (selector >= grp->extra_pin && selector < grp->extra_pin + grp->extra_npins) {
378 unsigned int reg = SELECTION;
379 unsigned int mask = grp->reg_mask;
380 int f, val;
381
382 val = (readl(info->base + reg) & mask);
383
384 for (f = 0; f < NB_FUNCS && grp->funcs[f]; f++) {
385 if (grp->val[f] == val) {
386 if (strcmp(grp->funcs[f], "gpio") != 0) {
387 strlcpy(buf, grp->funcs[f], size);
388 return 0;
389 }
390 break;
391 }
392 }
393 }
394 }
395
396 /* If pin is not active in some extra pin group then check regular groups. */
397 for (n = 0; n < info->data->ngroups; n++) {
398 struct armada_37xx_pin_group *grp = &info->data->groups[n];
399
400 if (selector >= grp->start_pin && selector < grp->start_pin + grp->npins) {
401 unsigned int reg = SELECTION;
402 unsigned int mask = grp->reg_mask;
403 int f, val;
404
405 val = (readl(info->base + reg) & mask);
406
407 for (f = 0; f < NB_FUNCS && grp->funcs[f]; f++) {
408 if (grp->val[f] == val) {
Pali Rohárd2dac1a2022-08-04 12:41:56 +0200409 /*
410 * In more cases group name consist of
411 * function name followed by function
412 * number. So if function name is just
413 * prefix of group name, show group name.
414 */
415 if (strncmp(grp->name, grp->funcs[f],
416 strlen(grp->funcs[f])) == 0)
417 strlcpy(buf, grp->name, size);
418 else
419 strlcpy(buf, grp->funcs[f], size);
Pali Rohárf6f0c092022-07-25 14:09:03 +0200420 return 0;
421 }
422 }
423
424 strlcpy(buf, "unknown", size);
425 return 0;
426 }
427 }
428
429 strlcpy(buf, "unknown", size);
430 return 0;
431}
432
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200433/**
434 * armada_37xx_add_function() - Add a new function to the list
435 * @funcs: array of function to add the new one
436 * @funcsize: size of the remaining space for the function
437 * @name: name of the function to add
438 *
439 * If it is a new function then create it by adding its name else
440 * increment the number of group associated to this function.
441 */
442static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
443 int *funcsize, const char *name)
444{
445 int i = 0;
446
447 if (*funcsize <= 0)
448 return -EOVERFLOW;
449
450 while (funcs->ngroups) {
451 /* function already there */
452 if (strcmp(funcs->name, name) == 0) {
453 funcs->ngroups++;
454
455 return -EEXIST;
456 }
457 funcs++;
458 i++;
459 }
460
461 /* append new unique function */
462 funcs->name = name;
463 funcs->ngroups = 1;
464 (*funcsize)--;
465
466 return 0;
467}
468
469/**
470 * armada_37xx_fill_group() - complete the group array
471 * @info: info driver instance
472 *
473 * Based on the data available from the armada_37xx_pin_group array
474 * completes the last member of the struct for each function: the list
475 * of the groups associated to this function.
476 *
477 */
478static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
479{
480 int n, num = 0, funcsize = info->data->nr_pins;
481
Pali Rohár579b5d62022-07-25 14:08:59 +0200482 for (n = 0; n < info->data->ngroups; n++) {
483 struct armada_37xx_pin_group *grp = &info->data->groups[n];
Pali Rohár34eff3f2022-07-25 14:08:58 +0200484 int f;
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200485
Ken Mab28aedb2018-03-26 15:56:01 +0800486 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200487 int ret;
488 /* check for unique functions and count groups */
489 ret = armada_37xx_add_function(info->funcs, &funcsize,
490 grp->funcs[f]);
491 if (ret == -EOVERFLOW)
492 dev_err(info->dev,
493 "More functions than pins(%d)\n",
494 info->data->nr_pins);
495 if (ret < 0)
496 continue;
497 num++;
498 }
499 }
500
501 info->nfuncs = num;
502
503 return 0;
504}
505
506/**
507 * armada_37xx_fill_funcs() - complete the funcs array
508 * @info: info driver instance
509 *
510 * Based on the data available from the armada_37xx_pin_group array
511 * completes the last two member of the struct for each group:
512 * - the list of the pins included in the group
513 * - the list of pinmux functions that can be selected for this group
514 *
515 */
516static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
517{
518 struct armada_37xx_pmx_func *funcs = info->funcs;
519 int n;
520
521 for (n = 0; n < info->nfuncs; n++) {
522 const char *name = funcs[n].name;
523 const char **groups;
524 int g;
525
526 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
527 sizeof(*(funcs[n].groups)),
528 GFP_KERNEL);
529 if (!funcs[n].groups)
530 return -ENOMEM;
531
532 groups = funcs[n].groups;
533
Pali Rohár579b5d62022-07-25 14:08:59 +0200534 for (g = 0; g < info->data->ngroups; g++) {
535 struct armada_37xx_pin_group *gp = &info->data->groups[g];
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200536 int f;
537
Ken Mab28aedb2018-03-26 15:56:01 +0800538 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200539 if (strcmp(gp->funcs[f], name) == 0) {
540 *groups = gp->name;
541 groups++;
542 }
543 }
544 }
545 }
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200546 return 0;
547}
548
549static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset)
550{
551 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
552 unsigned int reg = INPUT_VAL;
553 unsigned int val, mask;
554
Ken Maf72c5292018-03-26 15:56:02 +0800555 armada_37xx_update_reg(&reg, &offset);
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200556 mask = BIT(offset);
557
558 val = readl(info->base + reg);
559
560 return (val & mask) != 0;
561}
562
563static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset,
564 int value)
565{
566 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
567 unsigned int reg = OUTPUT_VAL;
568 unsigned int mask, val;
569
Ken Maf72c5292018-03-26 15:56:02 +0800570 armada_37xx_update_reg(&reg, &offset);
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200571 mask = BIT(offset);
572 val = value ? mask : 0;
573
574 clrsetbits_le32(info->base + reg, mask, val);
575
576 return 0;
577}
578
579static int armada_37xx_gpio_get_direction(struct udevice *dev,
580 unsigned int offset)
581{
582 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
583 unsigned int reg = OUTPUT_EN;
584 unsigned int val, mask;
585
Ken Maf72c5292018-03-26 15:56:02 +0800586 armada_37xx_update_reg(&reg, &offset);
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200587 mask = BIT(offset);
588 val = readl(info->base + reg);
589
590 if (val & mask)
591 return GPIOF_OUTPUT;
592 else
593 return GPIOF_INPUT;
594}
595
596static int armada_37xx_gpio_direction_input(struct udevice *dev,
597 unsigned int offset)
598{
599 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
600 unsigned int reg = OUTPUT_EN;
601 unsigned int mask;
602
Ken Maf72c5292018-03-26 15:56:02 +0800603 armada_37xx_update_reg(&reg, &offset);
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200604 mask = BIT(offset);
605
606 clrbits_le32(info->base + reg, mask);
607
608 return 0;
609}
610
611static int armada_37xx_gpio_direction_output(struct udevice *dev,
612 unsigned int offset, int value)
613{
614 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
615 unsigned int reg = OUTPUT_EN;
616 unsigned int mask;
617
Ken Maf72c5292018-03-26 15:56:02 +0800618 armada_37xx_update_reg(&reg, &offset);
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200619 mask = BIT(offset);
620
621 setbits_le32(info->base + reg, mask);
622
623 /* And set the requested value */
624 return armada_37xx_gpio_set(dev, offset, value);
625}
626
627static int armada_37xx_gpio_probe(struct udevice *dev)
628{
629 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
630 struct gpio_dev_priv *uc_priv;
631
632 uc_priv = dev_get_uclass_priv(dev);
633 uc_priv->bank_name = info->data->name;
634 uc_priv->gpio_count = info->data->nr_pins;
635
636 return 0;
637}
638
639static const struct dm_gpio_ops armada_37xx_gpio_ops = {
Pali Rohár9eaab3b2022-07-25 14:09:02 +0200640 .request = pinctrl_gpio_request,
641 .rfree = pinctrl_gpio_free,
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200642 .set_value = armada_37xx_gpio_set,
643 .get_value = armada_37xx_gpio_get,
644 .get_function = armada_37xx_gpio_get_direction,
645 .direction_input = armada_37xx_gpio_direction_input,
646 .direction_output = armada_37xx_gpio_direction_output,
647};
648
649static struct driver armada_37xx_gpio_driver = {
650 .name = "armada-37xx-gpio",
651 .id = UCLASS_GPIO,
652 .probe = armada_37xx_gpio_probe,
653 .ops = &armada_37xx_gpio_ops,
654};
655
656static int armada_37xx_gpiochip_register(struct udevice *parent,
657 struct armada_37xx_pinctrl *info)
658{
659 const void *blob = gd->fdt_blob;
660 int node = dev_of_offset(parent);
661 struct uclass_driver *drv;
662 struct udevice *dev;
663 int ret = -ENODEV;
664 int subnode;
665 char *name;
666
Simon Glass6996c662020-11-28 17:50:03 -0700667 /* FIXME: Should not need to lookup GPIO uclass */
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200668 drv = lists_uclass_lookup(UCLASS_GPIO);
669 if (!drv) {
670 puts("Cannot find GPIO driver\n");
671 return -ENOENT;
672 }
673
Simon Glass6996c662020-11-28 17:50:03 -0700674 /* FIXME: Use livtree and check the result of device_bind() below */
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200675 fdt_for_each_subnode(subnode, blob, node) {
Ken Mafeb93c62017-06-22 17:13:36 +0800676 if (fdtdec_get_bool(blob, subnode, "gpio-controller")) {
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200677 ret = 0;
678 break;
679 }
680 };
681 if (ret)
682 return ret;
683
684 name = calloc(1, 32);
685 sprintf(name, "armada-37xx-gpio");
686
687 /* Create child device UCLASS_GPIO and bind it */
Simon Glass6996c662020-11-28 17:50:03 -0700688 device_bind(parent, &armada_37xx_gpio_driver, name, NULL,
689 offset_to_ofnode(subnode), &dev);
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200690
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200691 return 0;
692}
693
Pali Rohár1497f2e2022-07-25 14:09:00 +0200694static const struct pinctrl_ops armada_37xx_pinctrl_ops = {
Pali Rohárf6f0c092022-07-25 14:09:03 +0200695 .get_pins_count = armada_37xx_pmx_get_pins_count,
696 .get_pin_name = armada_37xx_pmx_get_pin_name,
697 .get_pin_muxing = armada_37xx_pmx_get_pin_muxing,
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200698 .get_groups_count = armada_37xx_pmx_get_groups_count,
699 .get_group_name = armada_37xx_pmx_get_group_name,
700 .get_functions_count = armada_37xx_pmx_get_funcs_count,
701 .get_function_name = armada_37xx_pmx_get_func_name,
702 .pinmux_group_set = armada_37xx_pmx_group_set,
Pali Rohár9eaab3b2022-07-25 14:09:02 +0200703 .gpio_request_enable = armada_37xx_pmx_gpio_request_enable,
704 .gpio_disable_free = armada_37xx_pmx_gpio_disable_free,
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200705 .set_state = pinctrl_generic_set_state,
706};
707
Pali Rohár1497f2e2022-07-25 14:09:00 +0200708static int armada_37xx_pinctrl_probe(struct udevice *dev)
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200709{
710 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
711 const struct armada_37xx_pin_data *pin_data;
712 int ret;
713
714 info->data = (struct armada_37xx_pin_data *)dev_get_driver_data(dev);
715 pin_data = info->data;
716
Masahiro Yamada1096ae12020-07-17 14:36:46 +0900717 info->base = dev_read_addr_ptr(dev);
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200718 if (!info->base) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900719 pr_err("unable to find regmap\n");
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200720 return -ENODEV;
721 }
722
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200723 /*
724 * we allocate functions for number of pins and hope there are
725 * fewer unique functions than pins available
726 */
727 info->funcs = devm_kzalloc(info->dev, pin_data->nr_pins *
728 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
729 if (!info->funcs)
730 return -ENOMEM;
731
732
733 ret = armada_37xx_fill_group(info);
734 if (ret)
735 return ret;
736
737 ret = armada_37xx_fill_func(info);
738 if (ret)
739 return ret;
740
Gregory CLEMENT7ca5e2b2017-05-17 17:05:25 +0200741 ret = armada_37xx_gpiochip_register(dev, info);
742 if (ret)
743 return ret;
744
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200745 return 0;
746}
747
Robert Markoe3f26082023-01-17 15:08:15 +0100748static int armada_37xx_pinctrl_bind(struct udevice *dev)
749{
750 /*
751 * Make sure that the pinctrl driver gets probed after binding
752 * as on A37XX the pinctrl driver is the one that is also
753 * registering the GPIO one during probe, so if its not probed
754 * GPIO-s are not registered as well.
755 */
756 dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
757
758 return 0;
759}
760
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200761static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
762 {
763 .compatible = "marvell,armada3710-sb-pinctrl",
764 .data = (ulong)&armada_37xx_pin_sb,
765 },
766 {
767 .compatible = "marvell,armada3710-nb-pinctrl",
768 .data = (ulong)&armada_37xx_pin_nb,
769 },
770 { /* sentinel */ }
771};
772
773U_BOOT_DRIVER(armada_37xx_pinctrl) = {
774 .name = "armada-37xx-pinctrl",
775 .id = UCLASS_PINCTRL,
776 .of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
777 .probe = armada_37xx_pinctrl_probe,
Robert Markoe3f26082023-01-17 15:08:15 +0100778 .bind = armada_37xx_pinctrl_bind,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700779 .priv_auto = sizeof(struct armada_37xx_pinctrl),
Gregory CLEMENTa2490a22017-05-09 13:36:21 +0200780 .ops = &armada_37xx_pinctrl_ops,
781};