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git01.mediatek.com / filogic / uboot / ce7339cccb0be36457f3bc8a4d743387e37ff049 / . / arch / arm / dts / imx8mn-venice-gw7902.dts
blob: 29897c161b96dff3e34e9afc3148c9445bd70f45 [file] [log] [blame]
Tim Harvey1a50e742022-02-11 10:48:56 -0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/net/ti-dp83867.h>
12
13#include "imx8mn.dtsi"
14
15/ {
16 model = "Gateworks Venice GW7902 i.MX8MN board";
17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
18
19 aliases {
20 usb0 = &usbotg1;
21 };
22
23 chosen {
24 stdout-path = &uart2;
25 };
26
27 memory@40000000 {
28 device_type = "memory";
29 reg = <0x0 0x40000000 0 0x80000000>;
30 };
31
32 can20m: can20m {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <20000000>;
36 clock-output-names = "can20m";
37 };
38
39 gpio-keys {
40 compatible = "gpio-keys";
41
42 user-pb {
43 label = "user_pb";
44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
45 linux,code = <BTN_0>;
46 };
47
48 user-pb1x {
49 label = "user_pb1x";
50 linux,code = <BTN_1>;
51 interrupt-parent = <&gsc>;
52 interrupts = <0>;
53 };
54
55 key-erased {
56 label = "key_erased";
57 linux,code = <BTN_2>;
58 interrupt-parent = <&gsc>;
59 interrupts = <1>;
60 };
61
62 eeprom-wp {
63 label = "eeprom_wp";
64 linux,code = <BTN_3>;
65 interrupt-parent = <&gsc>;
66 interrupts = <2>;
67 };
68
69 tamper {
70 label = "tamper";
71 linux,code = <BTN_4>;
72 interrupt-parent = <&gsc>;
73 interrupts = <5>;
74 };
75
76 switch-hold {
77 label = "switch_hold";
78 linux,code = <BTN_5>;
79 interrupt-parent = <&gsc>;
80 interrupts = <7>;
81 };
82 };
83
84 led-controller {
85 compatible = "gpio-leds";
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_gpio_leds>;
88
89 led-0 {
90 function = LED_FUNCTION_STATUS;
91 color = <LED_COLOR_ID_GREEN>;
92 label = "panel1";
93 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
94 default-state = "off";
95 };
96
97 led-1 {
98 function = LED_FUNCTION_STATUS;
99 color = <LED_COLOR_ID_GREEN>;
100 label = "panel2";
101 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
102 default-state = "off";
103 };
104
105 led-2 {
106 function = LED_FUNCTION_STATUS;
107 color = <LED_COLOR_ID_GREEN>;
108 label = "panel3";
109 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
110 default-state = "off";
111 };
112
113 led-3 {
114 function = LED_FUNCTION_STATUS;
115 color = <LED_COLOR_ID_GREEN>;
116 label = "panel4";
117 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
118 default-state = "off";
119 };
120
121 led-4 {
122 function = LED_FUNCTION_STATUS;
123 color = <LED_COLOR_ID_GREEN>;
124 label = "panel5";
125 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
126 default-state = "off";
127 };
128 };
129
130 pps {
131 compatible = "pps-gpio";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_pps>;
134 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
135 status = "okay";
136 };
137
138 reg_3p3v: regulator-3p3v {
139 compatible = "regulator-fixed";
140 regulator-name = "3P3V";
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
143 };
144
145 reg_usb1_vbus: regulator-usb1 {
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_reg_usb1>;
148 compatible = "regulator-fixed";
149 regulator-name = "usb_usb1_vbus";
150 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
151 enable-active-high;
152 regulator-min-microvolt = <5000000>;
153 regulator-max-microvolt = <5000000>;
154 };
155
156 reg_wifi: regulator-wifi {
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_reg_wl>;
159 compatible = "regulator-fixed";
160 regulator-name = "wifi";
161 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
162 enable-active-high;
163 startup-delay-us = <100>;
164 regulator-min-microvolt = <3300000>;
165 regulator-max-microvolt = <3300000>;
166 };
167};
168
169&A53_0 {
170 cpu-supply = <&buck2>;
171};
172
173&A53_1 {
174 cpu-supply = <&buck2>;
175};
176
177&A53_2 {
178 cpu-supply = <&buck2>;
179};
180
181&A53_3 {
182 cpu-supply = <&buck2>;
183};
184
185&ddrc {
186 operating-points-v2 = <&ddrc_opp_table>;
187
188 ddrc_opp_table: opp-table {
189 compatible = "operating-points-v2";
190
191 opp-25M {
192 opp-hz = /bits/ 64 <25000000>;
193 };
194
195 opp-100M {
196 opp-hz = /bits/ 64 <100000000>;
197 };
198
199 opp-750M {
200 opp-hz = /bits/ 64 <750000000>;
201 };
202 };
203};
204
205&ecspi1 {
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_spi1>;
208 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
209 status = "okay";
210
211 can@0 {
212 compatible = "microchip,mcp2515";
213 reg = <0>;
214 clocks = <&can20m>;
215 oscillator-frequency = <20000000>;
216 interrupt-parent = <&gpio2>;
217 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
218 spi-max-frequency = <10000000>;
219 };
220};
221
222/* off-board header */
223&ecspi2 {
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_spi2>;
226 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
227 status = "okay";
228};
229
230&fec1 {
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_fec1>;
233 phy-mode = "rgmii-id";
234 phy-handle = <&ethphy0>;
235 local-mac-address = [00 00 00 00 00 00];
236 status = "okay";
237
238 mdio {
239 #address-cells = <1>;
240 #size-cells = <0>;
241
242 ethphy0: ethernet-phy@0 {
243 compatible = "ethernet-phy-ieee802.3-c22";
244 reg = <0>;
245 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
246 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
247 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
248 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
249 };
250 };
251};
252
253&i2c1 {
254 clock-frequency = <100000>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_i2c1>;
257 status = "okay";
258
259 gsc: gsc@20 {
260 compatible = "gw,gsc";
261 reg = <0x20>;
262 pinctrl-0 = <&pinctrl_gsc>;
263 interrupt-parent = <&gpio2>;
264 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
265 interrupt-controller;
266 #interrupt-cells = <1>;
267
268 adc {
269 compatible = "gw,gsc-adc";
270 #address-cells = <1>;
271 #size-cells = <0>;
272
273 channel@6 {
274 gw,mode = <0>;
275 reg = <0x06>;
276 label = "temp";
277 };
278
279 channel@8 {
280 gw,mode = <1>;
281 reg = <0x08>;
282 label = "vdd_bat";
283 };
284
285 channel@82 {
286 gw,mode = <2>;
287 reg = <0x82>;
288 label = "vin";
289 gw,voltage-divider-ohms = <22100 1000>;
290 gw,voltage-offset-microvolt = <700000>;
291 };
292
293 channel@84 {
294 gw,mode = <2>;
295 reg = <0x84>;
296 label = "vin_4p0";
297 gw,voltage-divider-ohms = <10000 10000>;
298 };
299
300 channel@86 {
301 gw,mode = <2>;
302 reg = <0x86>;
303 label = "vdd_3p3";
304 gw,voltage-divider-ohms = <10000 10000>;
305 };
306
307 channel@88 {
308 gw,mode = <2>;
309 reg = <0x88>;
310 label = "vdd_0p9";
311 };
312
313 channel@8c {
314 gw,mode = <2>;
315 reg = <0x8c>;
316 label = "vdd_soc";
317 };
318
319 channel@8e {
320 gw,mode = <2>;
321 reg = <0x8e>;
322 label = "vdd_arm";
323 };
324
325 channel@90 {
326 gw,mode = <2>;
327 reg = <0x90>;
328 label = "vdd_1p8";
329 };
330
331 channel@92 {
332 gw,mode = <2>;
333 reg = <0x92>;
334 label = "vdd_dram";
335 };
336
337 channel@98 {
338 gw,mode = <2>;
339 reg = <0x98>;
340 label = "vdd_1p0";
341 };
342
343 channel@9a {
344 gw,mode = <2>;
345 reg = <0x9a>;
346 label = "vdd_2p5";
347 gw,voltage-divider-ohms = <10000 10000>;
348 };
349
Tim Harveyf6d4bc42022-03-08 10:44:43 -0800[diff] [blame]350 channel@9c {
351 gw,mode = <2>;
352 reg = <0x9c>;
353 label = "vdd_5p0";
354 gw,voltage-divider-ohms = <10000 10000>;
355 };
356
Tim Harvey1a50e742022-02-11 10:48:56 -0800[diff] [blame]357 channel@a2 {
358 gw,mode = <2>;
359 reg = <0xa2>;
360 label = "vdd_gsc";
361 gw,voltage-divider-ohms = <10000 10000>;
362 };
363 };
364 };
365
366 gpio: gpio@23 {
367 compatible = "nxp,pca9555";
368 reg = <0x23>;
369 gpio-controller;
370 #gpio-cells = <2>;
371 interrupt-parent = <&gsc>;
372 interrupts = <4>;
373 };
374
375 pmic@4b {
376 compatible = "rohm,bd71847";
377 reg = <0x4b>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_pmic>;
380 interrupt-parent = <&gpio3>;
381 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
382 rohm,reset-snvs-powered;
383 #clock-cells = <0>;
384 clocks = <&osc_32k 0>;
385 clock-output-names = "clk-32k-out";
386
387 regulators {
388 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
389 BUCK1 {
390 regulator-name = "buck1";
391 regulator-min-microvolt = <700000>;
392 regulator-max-microvolt = <1300000>;
393 regulator-boot-on;
394 regulator-always-on;
395 regulator-ramp-delay = <1250>;
396 };
397
398 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
399 buck2: BUCK2 {
400 regulator-name = "buck2";
401 regulator-min-microvolt = <700000>;
402 regulator-max-microvolt = <1300000>;
403 regulator-boot-on;
404 regulator-always-on;
405 regulator-ramp-delay = <1250>;
406 rohm,dvs-run-voltage = <1000000>;
407 rohm,dvs-idle-voltage = <900000>;
408 };
409
410 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
411 BUCK3 {
412 regulator-name = "buck3";
413 regulator-min-microvolt = <700000>;
414 regulator-max-microvolt = <1350000>;
415 regulator-boot-on;
416 regulator-always-on;
417 };
418
419 /* vdd_3p3 */
420 BUCK4 {
421 regulator-name = "buck4";
422 regulator-min-microvolt = <3000000>;
423 regulator-max-microvolt = <3300000>;
424 regulator-boot-on;
425 regulator-always-on;
426 };
427
428 /* vdd_1p8 */
429 BUCK5 {
430 regulator-name = "buck5";
431 regulator-min-microvolt = <1605000>;
432 regulator-max-microvolt = <1995000>;
433 regulator-boot-on;
434 regulator-always-on;
435 };
436
437 /* vdd_dram */
438 BUCK6 {
439 regulator-name = "buck6";
440 regulator-min-microvolt = <800000>;
441 regulator-max-microvolt = <1400000>;
442 regulator-boot-on;
443 regulator-always-on;
444 };
445
446 /* nvcc_snvs_1p8 */
447 LDO1 {
448 regulator-name = "ldo1";
449 regulator-min-microvolt = <1600000>;
450 regulator-max-microvolt = <1900000>;
451 regulator-boot-on;
452 regulator-always-on;
453 };
454
455 /* vdd_snvs_0p8 */
456 LDO2 {
457 regulator-name = "ldo2";
458 regulator-min-microvolt = <800000>;
459 regulator-max-microvolt = <900000>;
460 regulator-boot-on;
461 regulator-always-on;
462 };
463
464 /* vdda_1p8 */
465 LDO3 {
466 regulator-name = "ldo3";
467 regulator-min-microvolt = <1800000>;
468 regulator-max-microvolt = <3300000>;
469 regulator-boot-on;
470 regulator-always-on;
471 };
472
473 LDO4 {
474 regulator-name = "ldo4";
475 regulator-min-microvolt = <900000>;
476 regulator-max-microvolt = <1800000>;
477 regulator-boot-on;
478 regulator-always-on;
479 };
480
481 LDO6 {
482 regulator-name = "ldo6";
483 regulator-min-microvolt = <900000>;
484 regulator-max-microvolt = <1800000>;
485 regulator-boot-on;
486 regulator-always-on;
487 };
488 };
489 };
490
491 eeprom@50 {
492 compatible = "atmel,24c02";
493 reg = <0x50>;
494 pagesize = <16>;
495 };
496
497 eeprom@51 {
498 compatible = "atmel,24c02";
499 reg = <0x51>;
500 pagesize = <16>;
501 };
502
503 eeprom@52 {
504 compatible = "atmel,24c02";
505 reg = <0x52>;
506 pagesize = <16>;
507 };
508
509 eeprom@53 {
510 compatible = "atmel,24c02";
511 reg = <0x53>;
512 pagesize = <16>;
513 };
514
515 rtc@68 {
516 compatible = "dallas,ds1672";
517 reg = <0x68>;
518 };
519};
520
521&i2c2 {
522 clock-frequency = <400000>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_i2c2>;
525 status = "okay";
526
527 accelerometer@19 {
528 pinctrl-names = "default";
529 pinctrl-0 = <&pinctrl_accel>;
530 compatible = "st,lis2de12";
531 reg = <0x19>;
532 st,drdy-int-pin = <1>;
533 interrupt-parent = <&gpio1>;
534 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
535 interrupt-names = "INT1";
536 };
537
538 secure-element@60 {
539 compatible = "nxp,se050";
540 reg = <0x60>;
541 };
542};
543
544/* off-board header */
545&i2c3 {
546 clock-frequency = <400000>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_i2c3>;
549 status = "okay";
550};
551
552/* off-board header */
553&i2c4 {
554 clock-frequency = <400000>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_i2c4>;
557 status = "okay";
558};
559
560/* off-board header */
561&sai3 {
562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_sai3>;
564 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
565 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
566 assigned-clock-rates = <24576000>;
567 status = "okay";
568};
569
570/* RS232/RS485/RS422 selectable */
571&uart1 {
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
574 status = "okay";
575};
576
577/* RS232 console */
578&uart2 {
579 pinctrl-names = "default";
580 pinctrl-0 = <&pinctrl_uart2>;
581 status = "okay";
582};
583
584/* bluetooth HCI */
585&uart3 {
586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
588 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
589 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
590 status = "okay";
591
592 bluetooth {
593 compatible = "brcm,bcm4330-bt";
594 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
595 };
596};
597
598/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
599&uart4 {
600 pinctrl-names = "default";
601 pinctrl-0 = <&pinctrl_uart4>;
602 status = "okay";
603};
604
605&usbotg1 {
606 dr_mode = "host";
607 vbus-supply = <&reg_usb1_vbus>;
608 disable-over-current;
609 status = "okay";
610};
611
612/* SDIO WiFi */
613&usdhc2 {
614 pinctrl-names = "default";
615 pinctrl-0 = <&pinctrl_usdhc2>;
616 bus-width = <4>;
617 non-removable;
618 vmmc-supply = <&reg_wifi>;
619 status = "okay";
620};
621
622/* eMMC */
623&usdhc3 {
624 pinctrl-names = "default", "state_100mhz", "state_200mhz";
625 pinctrl-0 = <&pinctrl_usdhc3>;
626 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
627 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
628 bus-width = <8>;
629 non-removable;
630 status = "okay";
631};
632
633&wdog1 {
634 pinctrl-names = "default";
635 pinctrl-0 = <&pinctrl_wdog>;
636 fsl,ext-reset-output;
637 status = "okay";
638};
639
640&iomuxc {
641 pinctrl-names = "default";
642 pinctrl-0 = <&pinctrl_hog>;
643
644 pinctrl_hog: hoggrp {
645 fsl,pins = <
646 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
647 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
648 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
649 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
650 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
651 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
652 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
653 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
654 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
655 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
656 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
657 >;
658 };
659
660 pinctrl_accel: accelgrp {
661 fsl,pins = <
662 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
663 >;
664 };
665
666 pinctrl_fec1: fec1grp {
667 fsl,pins = <
668 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
669 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
670 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
671 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
672 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
673 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
674 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
675 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
676 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
677 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
678 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
679 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
680 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
681 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
682 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
683 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
684 MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
685 MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
686 >;
687 };
688
689 pinctrl_gsc: gscgrp {
690 fsl,pins = <
691 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
692 >;
693 };
694
695 pinctrl_i2c1: i2c1grp {
696 fsl,pins = <
697 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
698 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
699 >;
700 };
701
702 pinctrl_i2c2: i2c2grp {
703 fsl,pins = <
704 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
705 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
706 >;
707 };
708
709 pinctrl_i2c3: i2c3grp {
710 fsl,pins = <
711 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
712 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
713 >;
714 };
715
716 pinctrl_i2c4: i2c4grp {
717 fsl,pins = <
718 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
719 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
720 >;
721 };
722
723 pinctrl_gpio_leds: gpioledgrp {
724 fsl,pins = <
725 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x40000019
726 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x40000019
727 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x40000019
728 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x40000019
729 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000019
730 >;
731 };
732
733 pinctrl_pmic: pmicgrp {
734 fsl,pins = <
735 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
736 >;
737 };
738
739 pinctrl_pps: ppsgrp {
740 fsl,pins = <
741 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
742 >;
743 };
744
745 pinctrl_reg_wl: regwlgrp {
746 fsl,pins = <
747 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
748 >;
749 };
750
751 pinctrl_reg_usb1: regusb1grp {
752 fsl,pins = <
753 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
754 >;
755 };
756
757 pinctrl_sai3: sai3grp {
758 fsl,pins = <
759 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
760 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
761 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
762 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
763 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
764 >;
765 };
766
767 pinctrl_spi1: spi1grp {
768 fsl,pins = <
769 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
770 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
771 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
772 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
773 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
774 >;
775 };
776
777 pinctrl_spi2: spi2grp {
778 fsl,pins = <
779 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
780 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
781 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
782 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
783 >;
784 };
785
786 pinctrl_uart1: uart1grp {
787 fsl,pins = <
788 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
789 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
790 >;
791 };
792
793 pinctrl_uart1_gpio: uart1gpiogrp {
794 fsl,pins = <
795 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
796 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
797 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
798 >;
799 };
800
801 pinctrl_uart2: uart2grp {
802 fsl,pins = <
803 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
804 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
805 >;
806 };
807
808 pinctrl_uart3_gpio: uart3_gpiogrp {
809 fsl,pins = <
810 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
811 >;
812 };
813
814 pinctrl_uart3: uart3grp {
815 fsl,pins = <
816 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
817 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
818 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
819 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
820 >;
821 };
822
823 pinctrl_uart4: uart4grp {
824 fsl,pins = <
825 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
826 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
827 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
828 >;
829 };
830
831 pinctrl_usdhc2: usdhc2grp {
832 fsl,pins = <
833 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
834 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
835 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
836 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
837 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
838 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
839 >;
840 };
841
842 pinctrl_usdhc3: usdhc3grp {
843 fsl,pins = <
844 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
845 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
846 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
847 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
848 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
849 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
850 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
851 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
852 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
853 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
854 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
855 >;
856 };
857
858 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
859 fsl,pins = <
860 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
861 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
862 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
863 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
864 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
865 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
866 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
867 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
868 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
869 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
870 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
871 >;
872 };
873
874 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
875 fsl,pins = <
876 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
877 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
878 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
879 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
880 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
881 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
882 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
883 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
884 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
885 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
886 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
887 >;
888 };
889
890 pinctrl_wdog: wdoggrp {
891 fsl,pins = <
892 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
893 >;
894 };
895};