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git01.mediatek.com / filogic / uboot / 3c8ef44cac3dac608a38fe1ff0d9fdad491e8f2d / . / cpu / mpc512x / fixed_sdram.c
blob: 673d61ee1005af04b84b7e846fd81f84d91495d9 [file] [log] [blame]
Wolfgang Denk1d7cc1e2009-06-14 20:58:47 +0200[diff] [blame]1/*
2 * (C) Copyright 2007-2009 DENX Software Engineering
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24#include <common.h>
25#include <asm/io.h>
26#include <asm/mpc512x.h>
27
28/*
Martha M Stanc12ecae2009-09-21 14:07:14 -0400[diff] [blame]29 * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers
30 */
31u32 default_mddrc_config[4] = {
32 CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */
33 CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */
34 CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */
35 CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */
36};
37
38u32 default_init_seq[] = {
39 CONFIG_SYS_DDRCMD_NOP,
40 CONFIG_SYS_DDRCMD_NOP,
41 CONFIG_SYS_DDRCMD_NOP,
42 CONFIG_SYS_DDRCMD_NOP,
43 CONFIG_SYS_DDRCMD_NOP,
44 CONFIG_SYS_DDRCMD_NOP,
45 CONFIG_SYS_DDRCMD_NOP,
46 CONFIG_SYS_DDRCMD_NOP,
47 CONFIG_SYS_DDRCMD_NOP,
48 CONFIG_SYS_DDRCMD_NOP,
49 CONFIG_SYS_DDRCMD_PCHG_ALL,
50 CONFIG_SYS_DDRCMD_NOP,
51 CONFIG_SYS_DDRCMD_RFSH,
52 CONFIG_SYS_DDRCMD_NOP,
53 CONFIG_SYS_DDRCMD_RFSH,
54 CONFIG_SYS_DDRCMD_NOP,
55 CONFIG_SYS_MICRON_INIT_DEV_OP,
56 CONFIG_SYS_DDRCMD_NOP,
57 CONFIG_SYS_DDRCMD_EM2,
58 CONFIG_SYS_DDRCMD_NOP,
59 CONFIG_SYS_DDRCMD_PCHG_ALL,
60 CONFIG_SYS_DDRCMD_EM2,
61 CONFIG_SYS_DDRCMD_EM3,
62 CONFIG_SYS_DDRCMD_EN_DLL,
63 CONFIG_SYS_MICRON_INIT_DEV_OP,
64 CONFIG_SYS_DDRCMD_PCHG_ALL,
65 CONFIG_SYS_DDRCMD_RFSH,
66 CONFIG_SYS_MICRON_INIT_DEV_OP,
67 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
68 CONFIG_SYS_DDRCMD_PCHG_ALL,
69 CONFIG_SYS_DDRCMD_NOP
70};
71
72/*
Wolfgang Denk1d7cc1e2009-06-14 20:58:47 +0200[diff] [blame]73 * fixed sdram init:
74 * The board doesn't use memory modules that have serial presence
75 * detect or similar mechanism for discovery of the DRAM settings
76 */
Martha M Stanc12ecae2009-09-21 14:07:14 -0400[diff] [blame]77long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz)
Wolfgang Denk1d7cc1e2009-06-14 20:58:47 +0200[diff] [blame]78{
79 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
80 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
81 u32 msize_log2 = __ilog2(msize);
82 u32 i;
83
Martha M Stanc12ecae2009-09-21 14:07:14 -0400[diff] [blame]84 /* take default settings and init sequence if necessary */
85 if (mddrc_config == NULL)
86 mddrc_config = default_mddrc_config;
87 if (dram_init_seq == NULL) {
88 dram_init_seq = default_init_seq;
89 seq_sz = sizeof(default_init_seq)/sizeof(u32);
90 }
91
Wolfgang Denk1d7cc1e2009-06-14 20:58:47 +0200[diff] [blame]92 /* Initialize IO Control */
93 out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
94
95 /* Initialize DDR Local Window */
96 out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
97 out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
98 sync_law(&im->sysconf.ddrlaw.ar);
99
Martha M Stanc12ecae2009-09-21 14:07:14 -0400[diff] [blame]100 /* DDR Enable */
101 out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN);
Wolfgang Denk1d7cc1e2009-06-14 20:58:47 +0200[diff] [blame]102
103 /* Initialize DDR Priority Manager */
104 out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
105 out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
106 out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
107 out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
108 out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
109 out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
110 out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
111 out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
112 out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
113 out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
114 out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
115 out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
116 out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
117 out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
118 out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
119 out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
120 out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
121 out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
122 out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
123 out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
124 out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
125 out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
126 out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
127
Martha M Stanc12ecae2009-09-21 14:07:14 -0400[diff] [blame]128 /*
129 * Initialize MDDRC
130 * put MDDRC in CMD mode and
131 * set the max time between refreshes to 0 during init process
132 */
133 out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK);
134 out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK);
135 out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]);
136 out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]);
Wolfgang Denk1d7cc1e2009-06-14 20:58:47 +0200[diff] [blame]137
Martha M Stanc12ecae2009-09-21 14:07:14 -0400[diff] [blame]138 /* Initialize DDR with either default or supplied init sequence */
139 for (i = 0; i < seq_sz; i++)
140 out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
Wolfgang Denk1d7cc1e2009-06-14 20:58:47 +0200[diff] [blame]141
142 /* Start MDDRC */
Martha M Stanc12ecae2009-09-21 14:07:14 -0400[diff] [blame]143 out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]);
144 out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]);
Wolfgang Denk1d7cc1e2009-06-14 20:58:47 +0200[diff] [blame]145
146 return msize;
147}