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git01.mediatek.com / filogic / uboot / 1d7cc1e353ff9b9c5a4645ee9d2fa0a43434042d / . / cpu / mpc512x / fixed_sdram.c
blob: d906903d28d104d25265f2ac752d89d5bfdcc12c [file] [log] [blame]
Wolfgang Denk1d7cc1e2009-06-14 20:58:47 +0200[diff] [blame^]1/*
2 * (C) Copyright 2007-2009 DENX Software Engineering
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24#include <common.h>
25#include <asm/io.h>
26#include <asm/mpc512x.h>
27
28/*
29 * fixed sdram init:
30 * The board doesn't use memory modules that have serial presence
31 * detect or similar mechanism for discovery of the DRAM settings
32 */
33long int fixed_sdram(void)
34{
35 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
36 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
37 u32 msize_log2 = __ilog2(msize);
38 u32 i;
39
40 /* Initialize IO Control */
41 out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
42
43 /* Initialize DDR Local Window */
44 out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
45 out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
46 sync_law(&im->sysconf.ddrlaw.ar);
47
48 /* Enable DDR */
49 out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
50
51 /* Initialize DDR Priority Manager */
52 out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
53 out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
54 out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
55 out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
56 out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
57 out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
58 out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
59 out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
60 out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
61 out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
62 out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
63 out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
64 out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
65 out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
66 out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
67 out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
68 out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
69 out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
70 out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
71 out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
72 out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
73 out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
74 out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
75
76 /* Initialize MDDRC */
77 out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
78 out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
79 out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
80 out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
81
82 /* Initialize DDR */
83 for (i = 0; i < 10; i++)
84 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
85
86 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
87 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
88 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
89 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
90 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
91 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
92 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
93 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
94 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
95 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
96 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
97 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
98 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
99 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
100 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
101 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
102 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
103 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
104 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
105 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
106 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
107
108 /* Start MDDRC */
109 out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
110 out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
111
112 return msize;
113}