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git01.mediatek.com / filogic / uboot / cde8c95e062c97c52a093ffaf6fc1c37c530ac3c / . / arch / arm / dts / sunxi-h3-h5-emlid-neutis.dtsi
blob: be5f5528a118320f217551f9c098b6707247c8f3 [file] [log] [blame]
Chen-Yu Tsai8d7da692020-01-12 23:36:13 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * DTSI for Emlid Neutis SoMs.
4 *
5 * Copyright (C) 2019 Georgii Staroselskii <georgii.staroselskii@emlid.com>
6 */
7
8#include "sunxi-common-regulators.dtsi"
9
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13 aliases {
14 serial0 = &uart0;
15 };
16
17 chosen {
18 stdout-path = "serial0:115200n8";
19 };
20
Andre Przywara3b798212024-04-19 17:59:52 +0100[diff] [blame]21 wifi_pwrseq: pwrseq {
Chen-Yu Tsai8d7da692020-01-12 23:36:13 +0800[diff] [blame]22 compatible = "mmc-pwrseq-simple";
23 reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
24 post-power-on-delay-ms = <200>;
Andre Przywarafa15e502022-09-13 00:52:52 +0100[diff] [blame]25 clocks = <&rtc CLK_OSC32K_FANOUT>;
Chen-Yu Tsai8d7da692020-01-12 23:36:13 +0800[diff] [blame]26 clock-names = "ext_clock";
27 };
28};
29
30&cpu0 {
31 cpu-supply = <&vdd_cpux>;
32};
33
34&reg_usb0_vbus {
35 gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
36 status = "okay";
37};
38
39
40&de {
41 status = "okay";
42};
43
44&ohci0 {
45 status = "okay";
46};
47
48&ohci1 {
49 status = "okay";
50};
51
52&ohci2 {
53 status = "okay";
54};
55
56&ohci3 {
57 status = "okay";
58};
59
60
61&ehci0 {
62 status = "okay";
63};
64
65&ehci1 {
66 status = "okay";
67};
68
69&ehci2 {
70 status = "okay";
71};
72
73&ehci3 {
74 status = "okay";
75};
76
77&mmc0 {
78 vmmc-supply = <&reg_vcc3v3>;
79 bus-width = <4>;
80 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
81 status = "okay";
82};
83
84
85&mmc1 {
86 vmmc-supply = <&reg_vcc3v3>;
87 vqmmc-supply = <&reg_vcc3v3>;
88 mmc-pwrseq = <&wifi_pwrseq>;
89 bus-width = <4>;
90 non-removable;
91 status = "okay";
92
93 brcmf: wifi@1 {
94 reg = <1>;
95 compatible = "brcm,bcm4329-fmac";
96 interrupt-parent = <&r_pio>;
97 interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */
98 interrupt-names = "host-wake";
99 };
100};
101
102&mmc2 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&mmc2_8bit_pins>;
105 vmmc-supply = <&reg_vcc3v3>;
106 bus-width = <8>;
107 non-removable;
108 cap-mmc-hw-reset;
109 status = "okay";
110};
111
112&uart0 {
113 pinctrl-names = "default";
114 pinctrl-0 = <&uart0_pa_pins>;
115 status = "okay";
116};
117
118
119&uart1 {
120 pinctrl-names = "default";
121 pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
122 uart-has-rtscts;
123 status = "okay";
124
125 bluetooth {
126 compatible = "brcm,bcm43438-bt";
Andre Przywarafa15e502022-09-13 00:52:52 +0100[diff] [blame]127 clocks = <&rtc CLK_OSC32K_FANOUT>;
Chen-Yu Tsai8d7da692020-01-12 23:36:13 +0800[diff] [blame]128 clock-names = "lpo";
129 vbat-supply = <&reg_vcc3v3>;
130 vddio-supply = <&reg_vcc3v3>;
131 shutdown-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
132 device-wakeup-gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
133 };
134};
135
136&uart2 {
137 pinctrl-names = "default";
138 pinctrl-0 = <&uart2_pins>;
139 status = "okay";
140};
141
142&uart3 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&uart3_pins>;
145 status = "okay";
146};
147
148&usbphy {
149 usb0_id_det-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
150 usb0_vbus-supply = <&reg_usb0_vbus>;
151 status = "okay";
152};
153
154&usb_otg {
155 dr_mode = "otg";
156 status = "okay";
157};
158
159&codec {
160 allwinner,audio-routing =
161 "Line Out", "LINEOUT",
162 "LINEIN", "Line In",
163 "MIC1", "Mic",
164 "MIC2", "Mic",
165 "Mic", "MBIAS";
166};
167
168&i2c0 {
169 status = "okay";
170};