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git01.mediatek.com / filogic / uboot / cde8c95e062c97c52a093ffaf6fc1c37c530ac3c / . / arch / arm / dts / qcom-ipq4019-u-boot.dtsi
blob: 07aaaa9f4172de464a49c9ad8d02d613c65586e4 [file] [log] [blame]
Robert Marko59843c32024-06-03 14:06:16 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/ {
3 soc {
4 switch: switch@c000000 {
5 compatible = "qcom,ipq4019-ess";
6 reg = <0xc000000 0x80000>, <0x98000 0x800>, <0xc080000 0x8000>;
7 reg-names = "base", "psgmii_phy", "edma";
8 resets = <&gcc ESS_PSGMII_ARES>, <&gcc ESS_RESET>;
9 reset-names = "psgmii", "ess";
10 clocks = <&gcc GCC_ESS_CLK>;
11 clock-names = "ess";
12 mdio = <&mdio>;
13 interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
14 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
15 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
16 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
17 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
18 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
19 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
20 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
21 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
22 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
23 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
24 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
25 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
26 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
27 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
28 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
29 <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
30 <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
31 <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
32 <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
33 <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
34 <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
35 <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
36 <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
37 <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
38 <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
39 <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
40 <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
41 <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
42 <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
43 <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
44 <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
45 status = "disabled";
46
47 ports {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 swport1: port@1 { /* MAC1 */
52 reg = <1>;
53 label = "lan1";
54 phy-handle = <&ethphy0>;
55 phy-mode = "psgmii";
56
57 status = "disabled";
58 };
59
60 swport2: port@2 { /* MAC2 */
61 reg = <2>;
62 label = "lan2";
63 phy-handle = <&ethphy1>;
64 phy-mode = "psgmii";
65
66 status = "disabled";
67 };
68
69 swport3: port@3 { /* MAC3 */
70 reg = <3>;
71 label = "lan3";
72 phy-handle = <&ethphy2>;
73 phy-mode = "psgmii";
74
75 status = "disabled";
76 };
77
78 swport4: port@4 { /* MAC4 */
79 reg = <4>;
80 label = "lan4";
81 phy-handle = <&ethphy3>;
82 phy-mode = "psgmii";
83
84 status = "disabled";
85 };
86
87 swport5: port@5 { /* MAC5 */
88 reg = <5>;
89 label = "wan";
90 phy-handle = <&ethphy4>;
91 phy-mode = "psgmii";
92
93 status = "disabled";
94 };
95 };
96 };
97 };
98};
99
100&mdio {
101 psgmiiphy: psgmii-phy@5 {
102 reg = <5>;
103 };
104};