| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2011 Samsung Electronics |
| 4 | * |
| Chander Kashyap | 4131a77 | 2011-12-06 23:34:12 +0000 | [diff] [blame] | 5 | * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board. |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
| Simon Glass | 05b3bac3 | 2014-10-07 22:01:49 -0600 | [diff] [blame] | 11 | #include "exynos4-common.h" |
| 12 | |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 13 | /* High Level Configuration Options */ |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 14 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 15 | |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 16 | /* Handling Sleep Mode*/ |
| 17 | #define S5P_CHECK_SLEEP 0x00000BAD |
| 18 | #define S5P_CHECK_DIDLE 0xBAD00000 |
| Rajeshwari Shinde | bed2442 | 2013-07-04 12:29:17 +0530 | [diff] [blame] | 19 | #define S5P_CHECK_LPA 0xABAD0000 |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 20 | |
| Chander Kashyap | 0cd984c | 2011-09-20 21:25:03 +0000 | [diff] [blame] | 21 | /* MMC SPL */ |
| Chander Kashyap | e8d043e | 2011-09-20 21:25:04 +0000 | [diff] [blame] | 22 | #define COPY_BL2_FNPTR_ADDR 0x00002488 |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 23 | |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 24 | /* SMDKV310 has 4 bank of DRAM */ |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 25 | #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 26 | #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 27 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 28 | #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 29 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 30 | #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 31 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 32 | #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 33 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE |
| 34 | |
| 35 | /* FLASH and environment organization */ |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 36 | |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 37 | /* Ethernet Controllor Driver */ |
| 38 | #ifdef CONFIG_CMD_NET |
| Tom Rini | 7e60cba | 2022-12-04 10:03:46 -0500 | [diff] [blame] | 39 | #define CFG_ENV_SROM_BANK 1 |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 40 | #endif /*CONFIG_CMD_NET*/ |
| Thomas Abraham | 4cd38a4 | 2011-06-03 22:52:17 +0000 | [diff] [blame] | 41 | |
| Chander Kashyap | bfef54d | 2011-05-24 20:02:56 +0000 | [diff] [blame] | 42 | #endif /* __CONFIG_H */ |