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git01.mediatek.com / filogic / uboot / cdc7ed3a93db92a264f0a6154693563a0c037f15 / . / arch / arm / dts / stm32mp15xx-dhcor-u-boot.dtsi
blob: 7529068c517ee22d395a8af2fb631a0310f47d9b [file] [log] [blame]
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2/*
3 * Copyright : STMicroelectronics 2018
4 *
5 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]7 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]8 */
9
10#include <dt-bindings/clock/stm32mp1-clksrc.h>
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]11#include "stm32mp15-u-boot.dtsi"
Marek Vasut272198e2020-04-29 15:08:38 +0200[diff] [blame]12#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
13#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
14#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]15
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]16/ {
17 u-boot,dm-pre-reloc;
18 config {
Marek Vasut39221b52020-04-22 13:18:14 +0200[diff] [blame]19 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]20 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
21 };
22};
23
Marek Vasutab56f882020-05-26 04:30:20 +0200[diff] [blame]24&gpiof {
25 snor-nwp {
26 gpio-hog;
27 gpios = <7 0>;
28 output-high;
29 line-name = "spi-nor-nwp";
30 };
31};
32
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]33&i2c4 {
34 u-boot,dm-pre-reloc;
35};
36
37&i2c4_pins_a {
38 u-boot,dm-pre-reloc;
39 pins {
40 u-boot,dm-pre-reloc;
41 };
42};
43
44&pmic {
45 u-boot,dm-pre-reloc;
46};
47
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]48&qspi {
49 u-boot,dm-spl;
50};
51
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]52&rcc {
53 st,clksrc = <
54 CLK_MPU_PLL1P
55 CLK_AXI_PLL2P
56 CLK_MCU_PLL3P
57 CLK_PLL12_HSE
58 CLK_PLL3_HSE
59 CLK_PLL4_HSE
60 CLK_RTC_LSE
61 CLK_MCO1_DISABLED
62 CLK_MCO2_DISABLED
63 >;
64
65 st,clkdiv = <
66 1 /*MPU*/
67 0 /*AXI*/
68 0 /*MCU*/
69 1 /*APB1*/
70 1 /*APB2*/
71 1 /*APB3*/
72 1 /*APB4*/
73 2 /*APB5*/
74 23 /*RTC*/
75 0 /*MCO1*/
76 0 /*MCO2*/
77 >;
78
79 st,pkcs = <
80 CLK_CKPER_HSE
81 CLK_FMC_ACLK
82 CLK_QSPI_ACLK
83 CLK_ETH_DISABLED
84 CLK_SDMMC12_PLL4P
85 CLK_DSI_DSIPLL
86 CLK_STGEN_HSE
87 CLK_USBPHY_HSE
88 CLK_SPI2S1_PLL3Q
89 CLK_SPI2S23_PLL3Q
90 CLK_SPI45_HSI
91 CLK_SPI6_HSI
92 CLK_I2C46_HSI
93 CLK_SDMMC3_PLL4P
94 CLK_USBO_USBPHY
95 CLK_ADC_CKPER
96 CLK_CEC_LSE
97 CLK_I2C12_HSI
98 CLK_I2C35_HSI
99 CLK_UART1_HSI
100 CLK_UART24_HSI
101 CLK_UART35_HSI
102 CLK_UART6_HSI
103 CLK_UART78_HSI
104 CLK_SPDIF_PLL4P
Antonio Borneo84159e82020-01-28 10:11:01 +0100[diff] [blame]105 CLK_FDCAN_PLL4R
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]106 CLK_SAI1_PLL3Q
107 CLK_SAI2_PLL3Q
108 CLK_SAI3_PLL3Q
109 CLK_SAI4_PLL3Q
110 CLK_RNG1_LSI
111 CLK_RNG2_LSI
112 CLK_LPTIM1_PCLK1
113 CLK_LPTIM23_PCLK3
114 CLK_LPTIM45_LSE
115 >;
116
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]117 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
118 pll2: st,pll@1 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]119 compatible = "st,stm32mp1-pll";
120 reg = <1>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]121 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
122 frac = < 0x1400 >;
123 u-boot,dm-pre-reloc;
124 };
125
126 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
127 pll3: st,pll@2 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]128 compatible = "st,stm32mp1-pll";
129 reg = <2>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]130 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
131 frac = < 0x1a04 >;
132 u-boot,dm-pre-reloc;
133 };
134
Marek Vasut787b17c2020-03-31 19:51:35 +0200[diff] [blame]135 /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]136 pll4: st,pll@3 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]137 compatible = "st,stm32mp1-pll";
138 reg = <3>;
Marek Vasut787b17c2020-03-31 19:51:35 +0200[diff] [blame]139 cfg = < 1 49 5 11 5 PQR(1,1,1) >;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]140 u-boot,dm-pre-reloc;
141 };
142};