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git01.mediatek.com / filogic / uboot / cd9e9985a3195ea6b040fc1c4b8fee39669673fc / . / board / xes / xpedite550x / tlb.c
blob: 7cb6cd677067566c6d1fb77b4a6bb9482ff3cc43 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]2/*
3 * Copyright 2008 Extreme Engineering Solutions, Inc.
4 * Copyright 2008 Freescale Semiconductor, Inc.
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]8 */
9
10#include <common.h>
11#include <asm/mmu.h>
12
13struct fsl_e_tlb_entry tlb_table[] = {
14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
26 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
27 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
28 MAS3_SX|MAS3_SW|MAS3_SR, 0,
29 0, 0, BOOKE_PAGESZ_4K, 0),
30
31 /* W**G* - NOR flashes */
32 /* This will be changed to *I*G* after relocation to RAM. */
33 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
34 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
35 0, 0, BOOKE_PAGESZ_256M, 1),
36
37 /* *I*G* - CCSRBAR */
38 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
39 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
40 0, 1, BOOKE_PAGESZ_1M, 1),
41
42 /* *I*G* - NAND flash */
43 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
44 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
45 0, 2, BOOKE_PAGESZ_1M, 1),
46
47 /* **M** - Boot page for secondary processors */
48 SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
49 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
50 0, 3, BOOKE_PAGESZ_4K, 1),
51
52#ifdef CONFIG_PCIE1
53 /* *I*G* - PCIe */
54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
55 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
56 0, 4, BOOKE_PAGESZ_1G, 1),
57#endif
58
59#ifdef CONFIG_PCIE2
60 /* *I*G* - PCIe */
61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
63 0, 5, BOOKE_PAGESZ_256M, 1),
64#endif
65
66#ifdef CONFIG_PCIE3
67 /* *I*G* - PCIe */
68 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
69 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
70 0, 6, BOOKE_PAGESZ_256M, 1),
71#endif
72
73#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
74 /* *I*G* - PCIe */
75 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
76 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
77 0, 7, BOOKE_PAGESZ_64M, 1),
78#endif
79};
80
81int num_tlb_entries = ARRAY_SIZE(tlb_table);