| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Shaohui Xie | dd33567 | 2015-11-11 17:58:37 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2015 Freescale Semiconductor, Inc. |
| Shaohui Xie | dd33567 | 2015-11-11 17:58:37 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __LS1043AQDS_QIXIS_H__ |
| 7 | #define __LS1043AQDS_QIXIS_H__ |
| 8 | |
| 9 | /* Definitions of QIXIS Registers for LS1043AQDS */ |
| 10 | |
| 11 | /* BRDCFG4[4:7] select EC1 and EC2 as a pair */ |
| 12 | #define BRDCFG4_EMISEL_MASK 0xe0 |
| 13 | #define BRDCFG4_EMISEL_SHIFT 5 |
| 14 | |
| 15 | /* SYSCLK */ |
| 16 | #define QIXIS_SYSCLK_66 0x0 |
| 17 | #define QIXIS_SYSCLK_83 0x1 |
| 18 | #define QIXIS_SYSCLK_100 0x2 |
| 19 | #define QIXIS_SYSCLK_125 0x3 |
| 20 | #define QIXIS_SYSCLK_133 0x4 |
| 21 | #define QIXIS_SYSCLK_150 0x5 |
| 22 | #define QIXIS_SYSCLK_160 0x6 |
| 23 | #define QIXIS_SYSCLK_166 0x7 |
| 24 | #define QIXIS_SYSCLK_64 0x8 |
| 25 | |
| 26 | /* DDRCLK */ |
| 27 | #define QIXIS_DDRCLK_66 0x0 |
| 28 | #define QIXIS_DDRCLK_100 0x1 |
| 29 | #define QIXIS_DDRCLK_125 0x2 |
| 30 | #define QIXIS_DDRCLK_133 0x3 |
| 31 | |
| 32 | /* BRDCFG2 - SD clock*/ |
| 33 | #define QIXIS_SDCLK1_100 0x0 |
| 34 | #define QIXIS_SDCLK1_125 0x1 |
| 35 | #define QIXIS_SDCLK1_165 0x2 |
| 36 | #define QIXIS_SDCLK1_100_SP 0x3 |
| 37 | |
| 38 | #endif |