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git01.mediatek.com / filogic / uboot / cd9e9985a3195ea6b040fc1c4b8fee39669673fc / . / board / d-link / dns325 / dns325.c
blob: a1d987bedaab7da406095a39064d86e719f69344 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]2/*
3 * Copyright (C) 2011
Stefan Herbrechtsmeier91eafc02014-12-28 14:09:50 +0100[diff] [blame]4 * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]5 *
6 * Based on Kirkwood support:
7 * (C) Copyright 2009
8 * Marvell Semiconductor <www.marvell.com>
9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]10 */
11
12#include <common.h>
13#include <miiphy.h>
14#include <netdev.h>
15#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]16#include <asm/arch/soc.h>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]17#include <asm/arch/mpp.h>
18#include <asm/arch/gpio.h>
19#include "dns325.h"
20
21DECLARE_GLOBAL_DATA_PTR;
22
23int board_early_init_f(void)
24{
25 /* Gpio configuration */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]26 mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
27 DNS325_OE_LOW, DNS325_OE_HIGH);
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]28
29 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]30 static const u32 kwmpp_config[] = {
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]31 MPP0_NF_IO2,
32 MPP1_NF_IO3,
33 MPP2_NF_IO4,
34 MPP3_NF_IO5,
35 MPP4_NF_IO6,
36 MPP5_NF_IO7,
37 MPP6_SYSRST_OUTn,
38 MPP7_GPO,
39 MPP8_TW_SDA,
40 MPP9_TW_SCK,
41 MPP10_UART0_TXD,
42 MPP11_UART0_RXD,
43 MPP12_SD_CLK,
44 MPP13_SD_CMD,
45 MPP14_SD_D0,
46 MPP15_SD_D1,
47 MPP16_SD_D2,
48 MPP17_SD_D3,
49 MPP18_NF_IO0,
50 MPP19_NF_IO1,
51 MPP20_SATA1_ACTn, /* sata1(left) status led */
52 MPP21_SATA0_ACTn, /* sata0(right) status led */
53 MPP22_GPIO,
54 MPP23_GPIO,
55 MPP24_GPIO, /* power off out */
56 MPP25_GPIO,
57 MPP26_GPIO, /* power led */
58 MPP27_GPIO, /* sata0(right) error led */
59 MPP28_GPIO, /* sata1(left) error led */
60 MPP29_GPIO, /* usb error led */
61 MPP30_GPIO,
62 MPP31_GPIO,
63 MPP32_GPIO,
64 MPP33_GPIO,
65 MPP34_GPIO, /* power key */
66 MPP35_GPIO,
67 MPP36_GPIO,
68 MPP37_GPIO,
69 MPP38_GPIO,
70 MPP39_GPIO, /* enable sata 0 */
71 MPP40_GPIO, /* enable sata 1 */
72 MPP41_GPIO, /* hdd0 present */
73 MPP42_GPIO, /* hdd1 present */
74 MPP43_GPIO, /* usb status led */
75 MPP44_GPIO, /* fan status */
76 MPP45_GPIO, /* fan high speed */
77 MPP46_GPIO, /* fan low speed */
78 MPP47_GPIO, /* usb umount */
79 MPP48_GPIO, /* factory reset */
80 MPP49_GPIO, /* thermal sensor */
81 0
82 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]83 kirkwood_mpp_conf(kwmpp_config, NULL);
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]84
85 kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
86
87 kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
88 return 0;
89}
90
91int board_init(void)
92{
93 /* Boot parameters address */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]94 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]95
96 return 0;
97}
98
99#ifdef CONFIG_RESET_PHY_R
100/* Configure and initialize PHY */
101void reset_phy(void)
102{
103 u16 reg;
104 u16 devadr;
105 char *name = "egiga0";
106
107 if (miiphy_set_current_dev(name))
108 return;
109
110 /* command to read PHY dev address */
111 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
112 printf("Err..(%s) could not read PHY dev address\n", __func__);
113 return;
114 }
115
116 /*
117 * Enable RGMII delay on Tx and Rx for CPU port
118 * Ref: sec 4.7.2 of chip datasheet
119 */
120 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
121 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
122 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
123 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
124 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
125
126 /* reset the phy */
127 miiphy_reset(name, devadr);
128
129 debug("88E1116 Initialized on %s\n", name);
130}
131#endif /* CONFIG_RESET_PHY_R */