blob: 524ed60903157fab43fab9b57408054cdb73080a [file] [log] [blame]
Kumar Gala3ab0b2d2008-08-12 11:13:08 -05001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
Tom Rinie2378802016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Kumar Gala3ab0b2d2008-08-12 11:13:08 -05005 */
6
7#include <common.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -05008
York Sunf0626592013-09-30 09:22:09 -07009#include <fsl_ddr_sdram.h>
10#include <fsl_ddr_dimm_params.h>
Kumar Gala3ab0b2d2008-08-12 11:13:08 -050011
York Sunb6d2ef62011-10-03 09:19:53 -070012struct board_specific_parameters {
Haiying Wangbcf35e52008-10-03 12:37:41 -040013 u32 n_ranks;
York Sunb6d2ef62011-10-03 09:19:53 -070014 u32 datarate_mhz_high;
Haiying Wangbcf35e52008-10-03 12:37:41 -040015 u32 clk_adjust;
16 u32 cpo;
17 u32 write_data_delay;
Priyanka Jain4a717412013-09-25 10:41:19 +053018 u32 force_2t;
York Sunb6d2ef62011-10-03 09:19:53 -070019};
Haiying Wangbcf35e52008-10-03 12:37:41 -040020
York Sun5e0c0702011-03-17 11:18:11 -070021/*
York Sunb6d2ef62011-10-03 09:19:53 -070022 * This table contains all valid speeds we want to override with board
23 * specific parameters. datarate_mhz_high values need to be in ascending order
24 * for each n_ranks group.
York Sun5e0c0702011-03-17 11:18:11 -070025 *
26 * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
27 * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
28 * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
29 * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
30 * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
York Sunb6d2ef62011-10-03 09:19:53 -070031 *
32 * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
Haiying Wangbcf35e52008-10-03 12:37:41 -040033 */
York Sunb6d2ef62011-10-03 09:19:53 -070034static const struct board_specific_parameters udimm0[] = {
York Sun5e0c0702011-03-17 11:18:11 -070035 /*
York Sunb6d2ef62011-10-03 09:19:53 -070036 * memory controller 0
37 * num| hi| clk| cpo|wrdata|2T
38 * ranks| mhz|adjst| | delay|
York Sun5e0c0702011-03-17 11:18:11 -070039 */
York Sunb6d2ef62011-10-03 09:19:53 -070040 {2, 333, 8, 7, 5, 0},
41 {2, 400, 8, 9, 5, 0},
42 {2, 549, 8, 11, 5, 0},
43 {2, 680, 8, 10, 5, 0},
44 {2, 850, 8, 12, 5, 1},
45 {1, 333, 6, 7, 3, 0},
46 {1, 400, 6, 9, 3, 0},
47 {1, 549, 6, 11, 3, 0},
48 {1, 680, 1, 10, 5, 0},
49 {1, 850, 1, 12, 5, 0},
50 {}
51};
Haiying Wangbcf35e52008-10-03 12:37:41 -040052
York Sunb6d2ef62011-10-03 09:19:53 -070053static const struct board_specific_parameters udimm1[] = {
York Sun5e0c0702011-03-17 11:18:11 -070054 /*
York Sunb6d2ef62011-10-03 09:19:53 -070055 * memory controller 1
56 * num| hi| clk| cpo|wrdata|2T
57 * ranks| mhz|adjst| | delay|
York Sun5e0c0702011-03-17 11:18:11 -070058 */
York Sunb6d2ef62011-10-03 09:19:53 -070059 {2, 333, 8, 7, 5, 0},
60 {2, 400, 8, 9, 5, 0},
61 {2, 549, 8, 11, 5, 0},
62 {2, 680, 8, 11, 5, 0},
63 {2, 850, 8, 13, 5, 1},
64 {1, 333, 6, 7, 3, 0},
65 {1, 400, 6, 9, 3, 0},
66 {1, 549, 6, 11, 3, 0},
67 {1, 680, 1, 11, 6, 0},
68 {1, 850, 1, 13, 6, 0},
69 {}
70};
71
72static const struct board_specific_parameters *udimms[] = {
73 udimm0,
74 udimm1,
Haiying Wangbcf35e52008-10-03 12:37:41 -040075};
76
York Sunb6d2ef62011-10-03 09:19:53 -070077static const struct board_specific_parameters rdimm0[] = {
York Sun5e0c0702011-03-17 11:18:11 -070078 /*
York Sunb6d2ef62011-10-03 09:19:53 -070079 * memory controller 0
80 * num| hi| clk| cpo|wrdata|2T
81 * ranks| mhz|adjst| | delay|
York Sun5e0c0702011-03-17 11:18:11 -070082 */
York Sunb6d2ef62011-10-03 09:19:53 -070083 {2, 333, 4, 7, 3, 0},
84 {2, 400, 4, 9, 3, 0},
85 {2, 549, 4, 11, 3, 0},
86 {2, 680, 4, 10, 3, 0},
87 {2, 850, 4, 12, 3, 1},
88 {}
89};
York Sun5e0c0702011-03-17 11:18:11 -070090
York Sunb6d2ef62011-10-03 09:19:53 -070091static const struct board_specific_parameters rdimm1[] = {
York Sun5e0c0702011-03-17 11:18:11 -070092 /*
York Sunb6d2ef62011-10-03 09:19:53 -070093 * memory controller 1
94 * num| hi| clk| cpo|wrdata|2T
95 * ranks| mhz|adjst| | delay|
York Sun5e0c0702011-03-17 11:18:11 -070096 */
York Sunb6d2ef62011-10-03 09:19:53 -070097 {2, 333, 4, 7, 3, 0},
98 {2, 400, 4, 9, 3, 0},
99 {2, 549, 4, 11, 3, 0},
100 {2, 680, 4, 11, 3, 0},
101 {2, 850, 4, 13, 3, 1},
102 {}
York Sun5e0c0702011-03-17 11:18:11 -0700103};
104
York Sunb6d2ef62011-10-03 09:19:53 -0700105static const struct board_specific_parameters *rdimms[] = {
106 rdimm0,
107 rdimm1,
108};
109
Haiying Wangfa440362008-10-03 12:36:55 -0400110void fsl_ddr_board_options(memctl_options_t *popts,
111 dimm_params_t *pdimm,
112 unsigned int ctrl_num)
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500113{
York Sunb6d2ef62011-10-03 09:19:53 -0700114 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
Haiying Wangbcf35e52008-10-03 12:37:41 -0400115 ulong ddr_freq;
York Sun5e0c0702011-03-17 11:18:11 -0700116
York Sunb6d2ef62011-10-03 09:19:53 -0700117 if (ctrl_num > 1) {
118 printf("Wrong parameter for controller number %d", ctrl_num);
York Sun5e0c0702011-03-17 11:18:11 -0700119 return;
York Sun5e0c0702011-03-17 11:18:11 -0700120 }
York Sunb6d2ef62011-10-03 09:19:53 -0700121 if (!pdimm->n_ranks)
122 return;
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500123
York Sunb6d2ef62011-10-03 09:19:53 -0700124 if (popts->registered_dimm_en)
125 pbsp = rdimms[ctrl_num];
126 else
127 pbsp = udimms[ctrl_num];
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500128
Haiying Wangbcf35e52008-10-03 12:37:41 -0400129 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
130 * freqency and n_banks specified in board_specific_parameters table.
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500131 */
Haiying Wangbcf35e52008-10-03 12:37:41 -0400132 ddr_freq = get_ddr_freq(0) / 1000000;
York Sunb6d2ef62011-10-03 09:19:53 -0700133 while (pbsp->datarate_mhz_high) {
134 if (pbsp->n_ranks == pdimm->n_ranks) {
135 if (ddr_freq <= pbsp->datarate_mhz_high) {
136 popts->clk_adjust = pbsp->clk_adjust;
137 popts->cpo_override = pbsp->cpo;
138 popts->write_data_delay =
139 pbsp->write_data_delay;
Priyanka Jain4a717412013-09-25 10:41:19 +0530140 popts->twot_en = pbsp->force_2t;
York Sunb6d2ef62011-10-03 09:19:53 -0700141 goto found;
142 }
143 pbsp_highest = pbsp;
Haiying Wangbcf35e52008-10-03 12:37:41 -0400144 }
145 pbsp++;
146 }
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500147
York Sunb6d2ef62011-10-03 09:19:53 -0700148 if (pbsp_highest) {
149 printf("Error: board specific timing not found "
150 "for data rate %lu MT/s!\n"
151 "Trying to use the highest speed (%u) parameters\n",
152 ddr_freq, pbsp_highest->datarate_mhz_high);
153 popts->clk_adjust = pbsp->clk_adjust;
154 popts->cpo_override = pbsp->cpo;
155 popts->write_data_delay = pbsp->write_data_delay;
Priyanka Jain4a717412013-09-25 10:41:19 +0530156 popts->twot_en = pbsp->force_2t;
York Sunb6d2ef62011-10-03 09:19:53 -0700157 } else {
158 panic("DIMM is not supported by this board");
York Sun24b66e52011-06-27 13:30:55 -0700159 }
York Sun5e0c0702011-03-17 11:18:11 -0700160
York Sunb6d2ef62011-10-03 09:19:53 -0700161found:
Kumar Gala3ab0b2d2008-08-12 11:13:08 -0500162 /*
163 * Factors to consider for half-strength driver enable:
164 * - number of DIMMs installed
165 */
166 popts->half_strength_driver_enable = 0;
167}