wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * Date & Time support for ST Electronics M48T35Ax RTC |
| 10 | */ |
| 11 | |
| 12 | /*#define DEBUG */ |
| 13 | |
| 14 | |
| 15 | #include <common.h> |
| 16 | #include <command.h> |
| 17 | #include <rtc.h> |
| 18 | #include <config.h> |
| 19 | |
Michal Simek | c3e6c55 | 2008-07-14 19:45:37 +0200 | [diff] [blame] | 20 | #if defined(CONFIG_CMD_DATE) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 21 | |
| 22 | static uchar rtc_read (uchar reg); |
| 23 | static void rtc_write (uchar reg, uchar val); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 24 | |
| 25 | /* ------------------------------------------------------------------------- */ |
| 26 | |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 27 | int rtc_get (struct rtc_time *tmp) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 28 | { |
| 29 | uchar sec, min, hour, cent_day, date, month, year; |
| 30 | uchar ccr; /* Clock control register */ |
| 31 | |
| 32 | /* Lock RTC for read using clock control register */ |
| 33 | ccr = rtc_read(0); |
| 34 | ccr = ccr | 0x40; |
| 35 | rtc_write(0, ccr); |
| 36 | |
| 37 | sec = rtc_read (0x1); |
| 38 | min = rtc_read (0x2); |
| 39 | hour = rtc_read (0x3); |
| 40 | cent_day= rtc_read (0x4); |
| 41 | date = rtc_read (0x5); |
| 42 | month = rtc_read (0x6); |
| 43 | year = rtc_read (0x7); |
| 44 | |
| 45 | /* UNLock RTC */ |
| 46 | ccr = rtc_read(0); |
| 47 | ccr = ccr & 0xBF; |
| 48 | rtc_write(0, ccr); |
| 49 | |
| 50 | debug ( "Get RTC year: %02x month: %02x date: %02x cent_day: %02x " |
| 51 | "hr: %02x min: %02x sec: %02x\n", |
| 52 | year, month, date, cent_day, |
| 53 | hour, min, sec ); |
| 54 | |
| 55 | tmp->tm_sec = bcd2bin (sec & 0x7F); |
| 56 | tmp->tm_min = bcd2bin (min & 0x7F); |
| 57 | tmp->tm_hour = bcd2bin (hour & 0x3F); |
| 58 | tmp->tm_mday = bcd2bin (date & 0x3F); |
| 59 | tmp->tm_mon = bcd2bin (month & 0x1F); |
| 60 | tmp->tm_year = bcd2bin (year) + ((cent_day & 0x10) ? 2000 : 1900); |
| 61 | tmp->tm_wday = bcd2bin (cent_day & 0x07); |
| 62 | tmp->tm_yday = 0; |
| 63 | tmp->tm_isdst= 0; |
| 64 | |
| 65 | debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
| 66 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 67 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 68 | |
| 69 | return 0; |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 70 | } |
| 71 | |
Jean-Christophe PLAGNIOL-VILLARD | 97a2e10 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 72 | int rtc_set (struct rtc_time *tmp) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 73 | { |
| 74 | uchar ccr; /* Clock control register */ |
| 75 | uchar century; |
| 76 | |
| 77 | debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
| 78 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 79 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
| 80 | |
| 81 | /* Lock RTC for write using clock control register */ |
| 82 | ccr = rtc_read(0); |
| 83 | ccr = ccr | 0x80; |
| 84 | rtc_write(0, ccr); |
| 85 | |
| 86 | rtc_write (0x07, bin2bcd(tmp->tm_year % 100)); |
| 87 | rtc_write (0x06, bin2bcd(tmp->tm_mon)); |
| 88 | rtc_write (0x05, bin2bcd(tmp->tm_mday)); |
| 89 | |
| 90 | century = ((tmp->tm_year >= 2000) ? 0x10 : 0) | 0x20; |
| 91 | rtc_write (0x04, bin2bcd(tmp->tm_wday) | century); |
| 92 | |
| 93 | rtc_write (0x03, bin2bcd(tmp->tm_hour)); |
| 94 | rtc_write (0x02, bin2bcd(tmp->tm_min )); |
| 95 | rtc_write (0x01, bin2bcd(tmp->tm_sec )); |
| 96 | |
| 97 | /* UNLock RTC */ |
| 98 | ccr = rtc_read(0); |
| 99 | ccr = ccr & 0x7F; |
| 100 | rtc_write(0, ccr); |
Jean-Christophe PLAGNIOL-VILLARD | 97a2e10 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 101 | |
| 102 | return 0; |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | void rtc_reset (void) |
| 106 | { |
| 107 | uchar val; |
| 108 | |
| 109 | /* Clear all clock control registers */ |
| 110 | rtc_write (0x0, 0x80); /* No Read Lock or calibration */ |
| 111 | |
| 112 | /* Clear stop bit */ |
| 113 | val = rtc_read (0x1); |
| 114 | val &= 0x7f; |
| 115 | rtc_write(0x1, val); |
| 116 | |
| 117 | /* Enable century / disable frequency test */ |
| 118 | val = rtc_read (0x4); |
| 119 | val = (val & 0xBF) | 0x20; |
| 120 | rtc_write(0x4, val); |
| 121 | |
| 122 | /* Clear write lock */ |
| 123 | rtc_write(0x0, 0); |
| 124 | } |
| 125 | |
| 126 | /* ------------------------------------------------------------------------- */ |
| 127 | |
| 128 | static uchar rtc_read (uchar reg) |
| 129 | { |
Masahiro Yamada | 30fe357 | 2016-09-06 22:17:39 +0900 | [diff] [blame] | 130 | return *(unsigned char *) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 131 | ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | static void rtc_write (uchar reg, uchar val) |
| 135 | { |
| 136 | *(unsigned char *) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 137 | ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val; |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 138 | } |
| 139 | |
Jon Loeliger | 07efe2a | 2007-07-10 10:27:39 -0500 | [diff] [blame] | 140 | #endif |