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git01.mediatek.com / filogic / uboot / cd817d510f82ebbe16498611b732060b337f3ca6 / . / drivers / rtc / max6900.c
blob: b35186579a5fa582528d5a81944f22898bb3e3d2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]2/*
3 * (C) Copyright 2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]5 */
6
7/*
8 * Date & Time support for MAXIM MAX6900 RTC
9 */
10
11/* #define DEBUG */
12
13#include <common.h>
14#include <command.h>
15#include <rtc.h>
16#include <i2c.h>
17
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]18#ifndef CONFIG_SYS_I2C_RTC_ADDR
19#define CONFIG_SYS_I2C_RTC_ADDR 0x50
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]20#endif
21
22/* ------------------------------------------------------------------------- */
23
24static uchar rtc_read (uchar reg)
25{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]26 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]27}
28
29static void rtc_write (uchar reg, uchar val)
30{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]31 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]32 udelay(2500);
33}
34
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]35/* ------------------------------------------------------------------------- */
36
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300[diff] [blame]37int rtc_get (struct rtc_time *tmp)
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]38{
39 uchar sec, min, hour, mday, wday, mon, cent, year;
40 int retry = 1;
41
42 do {
43 sec = rtc_read (0x80);
44 min = rtc_read (0x82);
45 hour = rtc_read (0x84);
46 mday = rtc_read (0x86);
47 mon = rtc_read (0x88);
48 wday = rtc_read (0x8a);
49 year = rtc_read (0x8c);
50 cent = rtc_read (0x92);
51 /*
52 * Check for seconds rollover
53 */
54 if ((sec != 59) || (rtc_read(0x80) == sec)){
55 retry = 0;
56 }
57 } while (retry);
58
59 debug ( "Get RTC year: %02x mon: %02x cent: %02x mday: %02x wday: %02x "
60 "hr: %02x min: %02x sec: %02x\n",
61 year, mon, cent, mday, wday,
62 hour, min, sec );
63
64 tmp->tm_sec = bcd2bin (sec & 0x7F);
65 tmp->tm_min = bcd2bin (min & 0x7F);
66 tmp->tm_hour = bcd2bin (hour & 0x3F);
67 tmp->tm_mday = bcd2bin (mday & 0x3F);
68 tmp->tm_mon = bcd2bin (mon & 0x1F);
69 tmp->tm_year = bcd2bin (year) + bcd2bin(cent) * 100;
70 tmp->tm_wday = bcd2bin (wday & 0x07);
71 tmp->tm_yday = 0;
72 tmp->tm_isdst= 0;
73
74 debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
75 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
76 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300[diff] [blame]77
78 return 0;
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]79}
80
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200[diff] [blame]81int rtc_set (struct rtc_time *tmp)
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]82{
83
84 debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
85 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
86 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
87
88 rtc_write (0x9E, 0x00);
89 rtc_write (0x80, 0); /* Clear seconds to ensure no rollover */
90 rtc_write (0x92, bin2bcd(tmp->tm_year / 100));
91 rtc_write (0x8c, bin2bcd(tmp->tm_year % 100));
92 rtc_write (0x8a, bin2bcd(tmp->tm_wday));
93 rtc_write (0x88, bin2bcd(tmp->tm_mon));
94 rtc_write (0x86, bin2bcd(tmp->tm_mday));
95 rtc_write (0x84, bin2bcd(tmp->tm_hour));
96 rtc_write (0x82, bin2bcd(tmp->tm_min ));
97 rtc_write (0x80, bin2bcd(tmp->tm_sec ));
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200[diff] [blame]98
99 return 0;
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]100}
101
102void rtc_reset (void)
103{
104}