| Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Texas Instruments, <www.ti.com> |
| 4 | * Aneesh V <aneesh@ti.com> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | #ifndef ARMV7_H |
| 25 | #define ARMV7_H |
| 26 | #include <linux/types.h> |
| 27 | |
| Aneesh V | 162ced3 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 28 | /* Cortex-A9 revisions */ |
| 29 | #define MIDR_CORTEX_A9_R0P1 0x410FC091 |
| 30 | #define MIDR_CORTEX_A9_R1P2 0x411FC092 |
| 31 | #define MIDR_CORTEX_A9_R1P3 0x411FC093 |
| Aneesh V | 0b92f09 | 2011-07-21 09:29:23 -0400 | [diff] [blame] | 32 | #define MIDR_CORTEX_A9_R2P10 0x412FC09A |
| Aneesh V | 162ced3 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 33 | |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 34 | /* Cortex-A15 revisions */ |
| 35 | #define MIDR_CORTEX_A15_R0P0 0x410FC0F0 |
| 36 | |
| Aneesh V | 960f5c0 | 2011-06-16 23:30:47 +0000 | [diff] [blame] | 37 | /* CCSIDR */ |
| 38 | #define CCSIDR_LINE_SIZE_OFFSET 0 |
| 39 | #define CCSIDR_LINE_SIZE_MASK 0x7 |
| 40 | #define CCSIDR_ASSOCIATIVITY_OFFSET 3 |
| 41 | #define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) |
| 42 | #define CCSIDR_NUM_SETS_OFFSET 13 |
| 43 | #define CCSIDR_NUM_SETS_MASK (0x7FFF << 13) |
| 44 | |
| 45 | /* |
| 46 | * Values for InD field in CSSELR |
| 47 | * Selects the type of cache |
| 48 | */ |
| 49 | #define ARMV7_CSSELR_IND_DATA_UNIFIED 0 |
| 50 | #define ARMV7_CSSELR_IND_INSTRUCTION 1 |
| 51 | |
| 52 | /* Values for Ctype fields in CLIDR */ |
| 53 | #define ARMV7_CLIDR_CTYPE_NO_CACHE 0 |
| 54 | #define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 |
| 55 | #define ARMV7_CLIDR_CTYPE_DATA_ONLY 2 |
| 56 | #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 |
| 57 | #define ARMV7_CLIDR_CTYPE_UNIFIED 4 |
| 58 | |
| 59 | /* |
| 60 | * CP15 Barrier instructions |
| 61 | * Please note that we have separate barrier instructions in ARMv7 |
| 62 | * However, we use the CP15 based instructtions because we use |
| 63 | * -march=armv5 in U-Boot |
| 64 | */ |
| 65 | #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) |
| 66 | #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) |
| 67 | #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) |
| 68 | |
| 69 | void v7_outer_cache_enable(void); |
| 70 | void v7_outer_cache_disable(void); |
| 71 | void v7_outer_cache_flush_all(void); |
| 72 | void v7_outer_cache_inval_all(void); |
| 73 | void v7_outer_cache_flush_range(u32 start, u32 end); |
| 74 | void v7_outer_cache_inval_range(u32 start, u32 end); |
| 75 | |
| 76 | #endif |