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git01.mediatek.com / filogic / uboot / cd51318861f885588ff3d0dee36c8e01555b1486 / . / dts / upstream / Bindings / media / mediatek,mt8195-jpegdec.yaml
blob: e5448c60e3eb5a2f067aa20be56514919666e794 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek JPEG Decoder
8
9maintainers:
10 - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
11
12description:
13 MediaTek JPEG Decoder is the JPEG decode hardware present in MediaTek SoCs
14
15properties:
16 compatible:
17 const: mediatek,mt8195-jpgdec
18
19 power-domains:
20 maxItems: 1
21
22 iommus:
23 maxItems: 6
24 description:
25 Points to the respective IOMMU block with master port as argument, see
26 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
27 Ports are according to the HW.
28
29 "#address-cells":
30 const: 2
31
32 "#size-cells":
33 const: 2
34
35 ranges: true
36
37# Required child node:
38patternProperties:
39 "^jpgdec@[0-9a-f]+$":
40 type: object
41 description:
42 The jpeg decoder hardware device node which should be added as subnodes to
43 the main jpeg node.
44
45 properties:
46 compatible:
47 const: mediatek,mt8195-jpgdec-hw
48
49 reg:
50 maxItems: 1
51
52 iommus:
53 minItems: 1
54 maxItems: 32
55 description:
56 List of the hardware port in respective IOMMU block for current Socs.
57 Refer to bindings/iommu/mediatek,iommu.yaml.
58
59 interrupts:
60 maxItems: 1
61
62 clocks:
63 maxItems: 1
64
65 clock-names:
66 items:
67 - const: jpgdec
68
69 power-domains:
70 maxItems: 1
71
72 required:
73 - compatible
74 - reg
75 - iommus
76 - interrupts
77 - clocks
78 - clock-names
79 - power-domains
80
81 additionalProperties: false
82
83required:
84 - compatible
85 - power-domains
86 - iommus
87 - ranges
88
89additionalProperties: false
90
91examples:
92 - |
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 #include <dt-bindings/memory/mt8195-memory-port.h>
95 #include <dt-bindings/interrupt-controller/irq.h>
96 #include <dt-bindings/clock/mt8195-clk.h>
97 #include <dt-bindings/power/mt8195-power.h>
98
99 soc {
100 #address-cells = <2>;
101 #size-cells = <2>;
102
103 jpgdec-master {
104 compatible = "mediatek,mt8195-jpgdec";
105 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
106 iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
107 <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
108 <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
109 <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
110 <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
111 <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
112 #address-cells = <2>;
113 #size-cells = <2>;
114 ranges;
115
116 jpgdec@1a040000 {
117 compatible = "mediatek,mt8195-jpgdec-hw";
118 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
119 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
120 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
121 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
122 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
123 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
124 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
125 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
126 clocks = <&vencsys CLK_VENC_JPGDEC>;
127 clock-names = "jpgdec";
128 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
129 };
130
131 jpgdec@1a050000 {
132 compatible = "mediatek,mt8195-jpgdec-hw";
133 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
134 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
135 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
136 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
137 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
138 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
139 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
140 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
141 clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
142 clock-names = "jpgdec";
143 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
144 };
145
146 jpgdec@1b040000 {
147 compatible = "mediatek,mt8195-jpgdec-hw";
148 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
149 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
150 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
151 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
152 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
153 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
154 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
155 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
156 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
157 clock-names = "jpgdec";
158 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
159 };
160 };
161 };