blob: 9deec47ae4623024c7610a50b13cfc203534c3ed [file] [log] [blame]
Frank Wang93543942023-05-29 13:01:33 +03001// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd
6 */
7
Frank Wang93543942023-05-29 13:01:33 +03008#include <clk.h>
9#include <dm.h>
10#include <dm/device_compat.h>
11#include <dm/devres.h>
12#include <dm/lists.h>
13#include <dm/of.h>
14#include <dm/of_access.h>
15#include <generic-phy.h>
16#include <linux/bitfield.h>
17#include <linux/usb/ch9.h>
18#include <linux/usb/otg.h>
19#include <regmap.h>
20#include <reset.h>
21#include <syscon.h>
22#include <asm/arch-rockchip/clock.h>
Jonas Karlmanc94fca32024-05-04 19:43:04 +000023#include <dt-bindings/phy/phy.h>
Frank Wang93543942023-05-29 13:01:33 +030024#include <linux/usb/phy-rockchip-usbdp.h>
25
26#define BIT_WRITEABLE_SHIFT 16
27
28enum {
29 UDPHY_MODE_NONE = 0,
30 UDPHY_MODE_USB = BIT(0),
31 UDPHY_MODE_DP = BIT(1),
32 UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
33};
34
35struct udphy_grf_reg {
36 unsigned int offset;
37 unsigned int bitend;
38 unsigned int bitstart;
39 unsigned int disable;
40 unsigned int enable;
41};
42
43/**
44 * struct reg_sequence - An individual write from a sequence of writes.
45 *
46 * @reg: Register address.
47 * @def: Register value.
48 * @delay_us: Delay to be applied after the register write in microseconds
49 *
50 * Register/value pairs for sequences of writes with an optional delay in
51 * microseconds to be applied after each write.
52 */
53struct reg_sequence {
54 unsigned int reg;
55 unsigned int def;
56 unsigned int delay_us;
57};
58
59struct udphy_grf_cfg {
60 /* u2phy-grf */
61 struct udphy_grf_reg bvalid_phy_con;
62 struct udphy_grf_reg bvalid_grf_con;
63
64 /* usb-grf */
65 struct udphy_grf_reg usb3otg0_cfg;
66 struct udphy_grf_reg usb3otg1_cfg;
67
68 /* usbdpphy-grf */
69 struct udphy_grf_reg low_pwrn;
70 struct udphy_grf_reg rx_lfps;
71};
72
73struct rockchip_udphy;
74
75struct rockchip_udphy_cfg {
Jonas Karlman4c17f662024-05-04 19:43:02 +000076 unsigned int num_phys;
77 unsigned int phy_ids[2];
Frank Wang93543942023-05-29 13:01:33 +030078 /* resets to be requested */
79 const char * const *rst_list;
80 int num_rsts;
81
82 struct udphy_grf_cfg grfcfg;
83 int (*combophy_init)(struct rockchip_udphy *udphy);
84};
85
86struct rockchip_udphy {
87 struct udevice *dev;
88 struct regmap *pma_regmap;
89 struct regmap *u2phygrf;
90 struct regmap *udphygrf;
91 struct regmap *usbgrf;
92 struct regmap *vogrf;
93
94 /* clocks and rests */
95 struct reset_ctl *rsts;
96
97 /* PHY status management */
98 bool flip;
99 bool mode_change;
100 u8 mode;
101 u8 status;
102
103 /* utilized for USB */
104 bool hs; /* flag for high-speed */
105
106 /* utilized for DP */
107 struct gpio_desc *sbu1_dc_gpio;
108 struct gpio_desc *sbu2_dc_gpio;
109 u32 lane_mux_sel[4];
110 u32 dp_lane_sel[4];
111 u32 dp_aux_dout_sel;
112 u32 dp_aux_din_sel;
113 int id;
114
115 /* PHY const config */
116 const struct rockchip_udphy_cfg *cfgs;
117};
118
119static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
120 {0x0090, 0x68}, {0x0094, 0x68},
121 {0x0128, 0x24}, {0x012c, 0x44},
122 {0x0130, 0x3f}, {0x0134, 0x44},
123 {0x015c, 0xa9}, {0x0160, 0x71},
124 {0x0164, 0x71}, {0x0168, 0xa9},
125 {0x0174, 0xa9}, {0x0178, 0x71},
126 {0x017c, 0x71}, {0x0180, 0xa9},
127 {0x018c, 0x41}, {0x0190, 0x00},
128 {0x0194, 0x05}, {0x01ac, 0x2a},
129 {0x01b0, 0x17}, {0x01b4, 0x17},
130 {0x01b8, 0x2a}, {0x01c8, 0x04},
131 {0x01cc, 0x08}, {0x01d0, 0x08},
132 {0x01d4, 0x04}, {0x01d8, 0x20},
133 {0x01dc, 0x01}, {0x01e0, 0x09},
134 {0x01e4, 0x03}, {0x01f0, 0x29},
135 {0x01f4, 0x02}, {0x01f8, 0x02},
136 {0x01fc, 0x29}, {0x0208, 0x2a},
137 {0x020c, 0x17}, {0x0210, 0x17},
138 {0x0214, 0x2a}, {0x0224, 0x20},
139 {0x03f0, 0x0d}, {0x03f4, 0x09},
140 {0x03f8, 0x09}, {0x03fc, 0x0d},
141 {0x0404, 0x0e}, {0x0408, 0x14},
142 {0x040c, 0x14}, {0x0410, 0x3b},
143 {0x0ce0, 0x68}, {0x0ce8, 0xd0},
144 {0x0cf0, 0x87}, {0x0cf8, 0x70},
145 {0x0d00, 0x70}, {0x0d08, 0xa9},
146 {0x1ce0, 0x68}, {0x1ce8, 0xd0},
147 {0x1cf0, 0x87}, {0x1cf8, 0x70},
148 {0x1d00, 0x70}, {0x1d08, 0xa9},
149 {0x0a3c, 0xd0}, {0x0a44, 0xd0},
150 {0x0a48, 0x01}, {0x0a4c, 0x0d},
151 {0x0a54, 0xe0}, {0x0a5c, 0xe0},
152 {0x0a64, 0xa8}, {0x1a3c, 0xd0},
153 {0x1a44, 0xd0}, {0x1a48, 0x01},
154 {0x1a4c, 0x0d}, {0x1a54, 0xe0},
155 {0x1a5c, 0xe0}, {0x1a64, 0xa8}
156};
157
158static const struct reg_sequence rk3588_udphy_init_sequence[] = {
159 {0x0104, 0x44}, {0x0234, 0xE8},
160 {0x0248, 0x44}, {0x028C, 0x18},
161 {0x081C, 0xE5}, {0x0878, 0x00},
162 {0x0994, 0x1C}, {0x0AF0, 0x00},
163 {0x181C, 0xE5}, {0x1878, 0x00},
164 {0x1994, 0x1C}, {0x1AF0, 0x00},
165 {0x0428, 0x60}, {0x0D58, 0x33},
166 {0x1D58, 0x33}, {0x0990, 0x74},
167 {0x0D64, 0x17}, {0x08C8, 0x13},
168 {0x1990, 0x74}, {0x1D64, 0x17},
169 {0x18C8, 0x13}, {0x0D90, 0x40},
170 {0x0DA8, 0x40}, {0x0DC0, 0x40},
171 {0x0DD8, 0x40}, {0x1D90, 0x40},
172 {0x1DA8, 0x40}, {0x1DC0, 0x40},
173 {0x1DD8, 0x40}, {0x03C0, 0x30},
174 {0x03C4, 0x06}, {0x0E10, 0x00},
175 {0x1E10, 0x00}, {0x043C, 0x0F},
176 {0x0D2C, 0xFF}, {0x1D2C, 0xFF},
177 {0x0D34, 0x0F}, {0x1D34, 0x0F},
178 {0x08FC, 0x2A}, {0x0914, 0x28},
179 {0x0A30, 0x03}, {0x0E38, 0x05},
180 {0x0ECC, 0x27}, {0x0ED0, 0x22},
181 {0x0ED4, 0x26}, {0x18FC, 0x2A},
182 {0x1914, 0x28}, {0x1A30, 0x03},
183 {0x1E38, 0x05}, {0x1ECC, 0x27},
184 {0x1ED0, 0x22}, {0x1ED4, 0x26},
185 {0x0048, 0x0F}, {0x0060, 0x3C},
186 {0x0064, 0xF7}, {0x006C, 0x20},
187 {0x0070, 0x7D}, {0x0074, 0x68},
188 {0x0AF4, 0x1A}, {0x1AF4, 0x1A},
189 {0x0440, 0x3F}, {0x10D4, 0x08},
190 {0x20D4, 0x08}, {0x00D4, 0x30},
191 {0x0024, 0x6e},
192};
193
194static inline int grfreg_write(struct regmap *base,
195 const struct udphy_grf_reg *reg, bool en)
196{
197 u32 val, mask, tmp;
198
199 tmp = en ? reg->enable : reg->disable;
200 mask = GENMASK(reg->bitend, reg->bitstart);
201 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
202
203 return regmap_write(base, reg->offset, val);
204}
205
206static int __regmap_multi_reg_write(struct regmap *map,
207 const struct reg_sequence *regs,
208 int num_regs)
209{
210 int i, ret = 0;
211
212 for (i = 0; i < num_regs; i++) {
213 ret = regmap_write(map, regs[i].reg, regs[i].def);
214
215 if (regs[i].delay_us)
216 udelay(regs[i].delay_us);
217 }
218
219 return ret;
220}
221
222static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev)
223{
224 return 0;
225}
226
227static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev)
228{
229 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
230 int idx;
231 int ret;
232
233 udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,
234 sizeof(*udphy->rsts), GFP_KERNEL);
235 if (!udphy->rsts)
236 return -ENOMEM;
237
238 for (idx = 0; idx < cfg->num_rsts; idx++) {
239 const char *name = cfg->rst_list[idx];
240
241 ret = reset_get_by_name(dev, name, &udphy->rsts[idx]);
242 if (ret) {
243 dev_err(dev, "failed to get %s reset\n", name);
244 goto err;
245 }
246
247 reset_assert(&udphy->rsts[idx]);
248 }
249
250 return 0;
251
252err:
253 devm_kfree(dev, udphy->rsts);
254 return ret;
255}
256
257static int udphy_get_rst_idx(const char * const *list, int num, char *name)
258{
259 int idx;
260
261 for (idx = 0; idx < num; idx++) {
262 if (!strcmp(list[idx], name))
263 return idx;
264 }
265
266 return -EINVAL;
267}
268
269static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)
270{
271 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
272 int idx;
273
274 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
275 if (idx < 0)
276 return idx;
277
278 return reset_assert(&udphy->rsts[idx]);
279}
280
281static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)
282{
283 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
284 int idx;
285
286 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
287 if (idx < 0)
288 return idx;
289
290 return reset_deassert(&udphy->rsts[idx]);
291}
292
293static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)
294{
295 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
296 const struct udphy_grf_reg *preg;
297
298 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
299 grfreg_write(udphy->usbgrf, preg, disable);
300}
301
302__maybe_unused
303static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)
304{
305 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
306
307 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
308 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
309}
310
311/*
312 * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
313 *
314 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
315 * ---------------------------------------------------------------------------
316 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
317 * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
318 * C/E(Normal) dpln3 dpln2 dpln0 dpln1
319 * C/E(Flip ) dpln0 dpln1 dpln3 dpln2
320 * D/F(Normal) usbrx usbtx dpln0 dpln1
321 * D/F(Flip ) dpln0 dpln1 usbrx usbtx
322 * A(Normal ) dpln3 dpln1 dpln2 dpln0
323 * A(Flip ) dpln2 dpln0 dpln3 dpln1
324 * B(Normal ) usbrx usbtx dpln1 dpln0
325 * B(Flip ) dpln1 dpln0 usbrx usbtx
326 * ---------------------------------------------------------------------------
327 *
328 * 2 Mapping the lanes in dtsi
329 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
330 * sample as follow:
331 * ---------------------------------------------------------------------------
332 * B11-B10 A2-A3 A11-A10 B2-B3
333 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
334 * <0 1 2 3> dpln0 dpln1 dpln2 dpln3
335 * <2 3 0 1> dpln2 dpln3 dpln0 dpln1
336 * ---------------------------------------------------------------------------
337 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
338 * sample as follow:
339 * ---------------------------------------------------------------------------
340 * B11-B10 A2-A3 A11-A10 B2-B3
341 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
342 * <0 1> dpln0 dpln1 usbrx usbtx
343 * <2 3> usbrx usbtx dpln0 dpln1
344 * ---------------------------------------------------------------------------
345 */
346
347__maybe_unused
348static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy)
349{
350 if (udphy->flip) {
351 udphy->dp_lane_sel[0] = 0;
352 udphy->dp_lane_sel[1] = 1;
353 udphy->dp_lane_sel[2] = 3;
354 udphy->dp_lane_sel[3] = 2;
355 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
356 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
357 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
358 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
359 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
360 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
361 } else {
362 udphy->dp_lane_sel[0] = 2;
363 udphy->dp_lane_sel[1] = 3;
364 udphy->dp_lane_sel[2] = 1;
365 udphy->dp_lane_sel[3] = 0;
366 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
367 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
368 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
369 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
370 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
371 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
372 }
373
374 udphy->mode = UDPHY_MODE_DP_USB;
375
376 return 0;
377}
378
379static int udphy_setup(struct rockchip_udphy *udphy)
380{
381 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
382 int ret = 0;
383
384 if (cfg->combophy_init) {
385 ret = cfg->combophy_init(udphy);
386 if (ret)
387 dev_err(udphy->dev, "failed to init usbdp combophy\n");
388 }
389
390 return ret;
391}
392
393static int udphy_disable(struct rockchip_udphy *udphy)
394{
395 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
396 int i;
397
398 for (i = 0; i < cfg->num_rsts; i++)
399 reset_assert(&udphy->rsts[i]);
400
401 return 0;
402}
403
404static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy,
405 const struct device_node *np)
406{
407 struct property *prop;
408 int ret, i, len, num_lanes;
409
410 prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
411 if (!prop) {
412 dev_dbg(udphy->dev,
413 "failed to find dp lane mux, following dp alt mode\n");
414 udphy->mode = UDPHY_MODE_USB;
415 return 0;
416 }
417
418 num_lanes = len / sizeof(u32);
419
420 if (num_lanes != 2 && num_lanes != 4) {
421 dev_err(udphy->dev, "invalid number of lane mux\n");
422 return -EINVAL;
423 }
424
425 ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel,
426 num_lanes);
427 if (ret) {
428 dev_err(udphy->dev, "get dp lane mux failed\n");
429 return -EINVAL;
430 }
431
432 for (i = 0; i < num_lanes; i++) {
433 int j;
434
435 if (udphy->dp_lane_sel[i] > 3) {
436 dev_err(udphy->dev,
437 "lane mux between 0 and 3, exceeding the range\n");
438 return -EINVAL;
439 }
440
441 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
442
443 for (j = i + 1; j < num_lanes; j++) {
444 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
445 dev_err(udphy->dev,
446 "set repeat lane mux value\n");
447 return -EINVAL;
448 }
449 }
450 }
451
452 udphy->mode = UDPHY_MODE_DP;
453 if (num_lanes == 2)
454 udphy->mode |= UDPHY_MODE_USB;
455
456 return 0;
457}
458
459static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
460{
461 const struct device_node *np = ofnode_to_np(dev_ofnode(dev));
462 enum usb_device_speed maximum_speed;
463 int ret;
464
465 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev,
466 "rockchip,u2phy-grf");
467 if (IS_ERR(udphy->u2phygrf)) {
468 if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {
469 dev_warn(dev, "missing u2phy-grf dt node\n");
470 udphy->u2phygrf = NULL;
471 } else {
472 return PTR_ERR(udphy->u2phygrf);
473 }
474 }
475
476 udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev,
477 "rockchip,usbdpphy-grf");
478 if (IS_ERR(udphy->udphygrf)) {
479 if (PTR_ERR(udphy->udphygrf) == -ENODEV) {
480 dev_warn(dev, "missing usbdpphy-grf dt node\n");
481 udphy->udphygrf = NULL;
482 } else {
483 return PTR_ERR(udphy->udphygrf);
484 }
485 }
486
487 udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev,
488 "rockchip,usb-grf");
489 if (IS_ERR(udphy->usbgrf)) {
490 if (PTR_ERR(udphy->usbgrf) == -ENODEV) {
491 dev_warn(dev, "missing usb-grf dt node\n");
492 udphy->usbgrf = NULL;
493 } else {
494 return PTR_ERR(udphy->usbgrf);
495 }
496 }
497
498 udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf");
499 if (IS_ERR(udphy->vogrf)) {
500 if (PTR_ERR(udphy->vogrf) == -ENODEV) {
501 dev_warn(dev, "missing vo-grf dt node\n");
502 udphy->vogrf = NULL;
503 } else {
504 return PTR_ERR(udphy->vogrf);
505 }
506 }
507
508 ret = udphy_parse_lane_mux_data(udphy, np);
509 if (ret)
510 return ret;
511
512 if (dev_read_prop(dev, "maximum-speed", NULL)) {
513 maximum_speed = usb_get_maximum_speed(dev_ofnode(dev));
514 udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
515 }
516
517 ret = udphy_clk_init(udphy, dev);
518 if (ret)
519 return ret;
520
521 ret = udphy_reset_init(udphy, dev);
522 if (ret)
523 return ret;
524
525 return 0;
526}
527
528static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
529{
530 int ret;
531
532 if (!(udphy->mode & mode)) {
533 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
534 return 0;
535 }
536
537 if (udphy->status == UDPHY_MODE_NONE) {
538 udphy->mode_change = false;
539 ret = udphy_setup(udphy);
540 if (ret)
541 return ret;
542
543 if (udphy->mode & UDPHY_MODE_USB)
544 udphy_u3_port_disable(udphy, false);
545 } else if (udphy->mode_change) {
546 udphy->mode_change = false;
547 udphy->status = UDPHY_MODE_NONE;
548 if (udphy->mode == UDPHY_MODE_DP)
549 udphy_u3_port_disable(udphy, true);
550
551 ret = udphy_disable(udphy);
552 if (ret)
553 return ret;
554 ret = udphy_setup(udphy);
555 if (ret)
556 return ret;
557 }
558
559 udphy->status |= mode;
560
561 return 0;
562}
563
564static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
565{
566 int ret;
567
568 if (!(udphy->mode & mode)) {
569 dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode);
570 return 0;
571 }
572
573 if (!udphy->status)
574 return 0;
575
576 udphy->status &= ~mode;
577
578 if (udphy->status == UDPHY_MODE_NONE) {
579 ret = udphy_disable(udphy);
580 if (ret)
581 return ret;
582 }
583
584 return 0;
585}
586
Jonas Karlmanc94fca32024-05-04 19:43:04 +0000587static int rockchip_u3phy_of_xlate(struct phy *phy,
588 struct ofnode_phandle_args *args)
589{
590 if (args->args_count == 0)
591 return -EINVAL;
592
593 if (args->args[0] != PHY_TYPE_USB3)
594 return -EINVAL;
595
596 return 0;
597}
598
Frank Wang93543942023-05-29 13:01:33 +0300599static int rockchip_u3phy_init(struct phy *phy)
600{
Jonas Karlmanc94fca32024-05-04 19:43:04 +0000601 struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
Frank Wang93543942023-05-29 13:01:33 +0300602
603 /* DP only or high-speed, disable U3 port */
604 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
605 udphy_u3_port_disable(udphy, true);
606 return 0;
607 }
608
609 return udphy_power_on(udphy, UDPHY_MODE_USB);
610}
611
612static int rockchip_u3phy_exit(struct phy *phy)
613{
Jonas Karlmanc94fca32024-05-04 19:43:04 +0000614 struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
Frank Wang93543942023-05-29 13:01:33 +0300615
616 /* DP only or high-speed */
617 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
618 return 0;
619
620 return udphy_power_off(udphy, UDPHY_MODE_USB);
621}
622
623static const struct phy_ops rockchip_u3phy_ops = {
Jonas Karlmanc94fca32024-05-04 19:43:04 +0000624 .of_xlate = rockchip_u3phy_of_xlate,
Frank Wang93543942023-05-29 13:01:33 +0300625 .init = rockchip_u3phy_init,
626 .exit = rockchip_u3phy_exit,
627};
628
Frank Wang93543942023-05-29 13:01:33 +0300629static int rockchip_udphy_probe(struct udevice *dev)
630{
Frank Wang93543942023-05-29 13:01:33 +0300631 struct rockchip_udphy *udphy = dev_get_priv(dev);
632 const struct rockchip_udphy_cfg *phy_cfgs;
Jonas Karlman4c17f662024-05-04 19:43:02 +0000633 unsigned int reg;
Frank Wang93543942023-05-29 13:01:33 +0300634 int id, ret;
635
636 udphy->dev = dev;
637
Jonas Karlman4c17f662024-05-04 19:43:02 +0000638 ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, &reg);
639 if (ret) {
640 dev_err(dev, "failed to read reg[0] property\n");
641 return ret;
642 }
643 if (reg == 0 && dev_read_addr_cells(dev) == 2) {
644 ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, &reg);
645 if (ret) {
646 dev_err(dev, "failed to read reg[1] property\n");
647 return ret;
648 }
649 }
Frank Wang93543942023-05-29 13:01:33 +0300650
651 phy_cfgs = (const struct rockchip_udphy_cfg *)dev_get_driver_data(dev);
652 if (!phy_cfgs) {
653 dev_err(dev, "unable to get phy_cfgs\n");
654 return -EINVAL;
655 }
656 udphy->cfgs = phy_cfgs;
657
Jonas Karlman4c17f662024-05-04 19:43:02 +0000658 /* find the phy-id from the io address */
659 udphy->id = -ENODEV;
660 for (id = 0; id < udphy->cfgs->num_phys; id++) {
661 if (reg == udphy->cfgs->phy_ids[id]) {
662 udphy->id = id;
663 break;
664 }
665 }
666
667 if (udphy->id < 0) {
668 dev_err(dev, "no matching device found\n");
669 return -ENODEV;
670 }
671
Frank Wang93543942023-05-29 13:01:33 +0300672 ret = regmap_init_mem(dev_ofnode(dev), &udphy->pma_regmap);
673 if (ret)
674 return ret;
675 udphy->pma_regmap->ranges[0].start += UDPHY_PMA;
676
677 ret = udphy_parse_dt(udphy, dev);
678 if (ret)
679 return ret;
680
681 return 0;
682}
683
Frank Wang93543942023-05-29 13:01:33 +0300684static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
685{
686 /* configure phy reference clock */
687 return __regmap_multi_reg_write(udphy->pma_regmap,
688 rk3588_udphy_24m_refclk_cfg,
689 ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg));
690}
691
692static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)
693{
694 unsigned int val;
695 int ret;
696
697 if (!(udphy->mode & UDPHY_MODE_USB))
698 return 0;
699
700 /* LCPLL check */
701 ret = regmap_read_poll_timeout(udphy->pma_regmap,
702 CMN_ANA_LCPLL_DONE_OFFSET,
703 val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
704 (val & CMN_ANA_LCPLL_LOCK_DONE),
705 200, 100);
706 if (ret) {
707 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
708 return ret;
709 }
710
711 if (!udphy->flip) {
712 ret = regmap_read_poll_timeout(udphy->pma_regmap,
713 TRSV_LN0_MON_RX_CDR_DONE_OFFSET,
714 val,
715 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
716 200, 100);
717 if (ret)
718 dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
719 } else {
720 ret = regmap_read_poll_timeout(udphy->pma_regmap,
721 TRSV_LN2_MON_RX_CDR_DONE_OFFSET,
722 val,
723 val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
724 200, 100);
725 if (ret)
726 dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
727 }
728
729 return 0;
730}
731
732static int rk3588_udphy_init(struct rockchip_udphy *udphy)
733{
734 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
735 int ret;
736
737 /* enable rx lfps for usb */
738 if (udphy->mode & UDPHY_MODE_USB)
739 grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
740
741 /* Step 1: power on pma and deassert apb rstn */
742 grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
743
744 udphy_reset_deassert(udphy, "pma_apb");
745 udphy_reset_deassert(udphy, "pcs_apb");
746
747 /* Step 2: set init sequence and phy refclk */
748 ret = __regmap_multi_reg_write(udphy->pma_regmap,
749 rk3588_udphy_init_sequence,
750 ARRAY_SIZE(rk3588_udphy_init_sequence));
751 if (ret) {
752 dev_err(udphy->dev, "init sequence set error %d\n", ret);
753 goto assert_apb;
754 }
755
756 ret = rk3588_udphy_refclk_set(udphy);
757 if (ret) {
758 dev_err(udphy->dev, "refclk set error %d\n", ret);
759 goto assert_apb;
760 }
761
762 /* Step 3: configure lane mux */
763 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
764 CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
765 FIELD_PREP(CMN_DP_LANE_MUX_N(3),
766 udphy->lane_mux_sel[3]) |
767 FIELD_PREP(CMN_DP_LANE_MUX_N(2),
768 udphy->lane_mux_sel[2]) |
769 FIELD_PREP(CMN_DP_LANE_MUX_N(1),
770 udphy->lane_mux_sel[1]) |
771 FIELD_PREP(CMN_DP_LANE_MUX_N(0),
772 udphy->lane_mux_sel[0]) |
773 FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
774
775 /* Step 4: deassert init rstn and wait for 200ns from datasheet */
776 if (udphy->mode & UDPHY_MODE_USB)
777 udphy_reset_deassert(udphy, "init");
778
779 if (udphy->mode & UDPHY_MODE_DP) {
780 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
781 CMN_DP_INIT_RSTN,
782 FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
783 }
784
785 udelay(1);
786
787 /* Step 5: deassert cmn/lane rstn */
788 if (udphy->mode & UDPHY_MODE_USB) {
789 udphy_reset_deassert(udphy, "cmn");
790 udphy_reset_deassert(udphy, "lane");
791 }
792
793 /* Step 6: wait for lock done of pll */
794 ret = rk3588_udphy_status_check(udphy);
795 if (ret)
796 goto assert_phy;
797
798 return 0;
799
800assert_phy:
801 udphy_reset_assert(udphy, "init");
802 udphy_reset_assert(udphy, "cmn");
803 udphy_reset_assert(udphy, "lane");
804
805assert_apb:
806 udphy_reset_assert(udphy, "pma_apb");
807 udphy_reset_assert(udphy, "pcs_apb");
808
809 return ret;
810}
811
812static const char * const rk3588_udphy_rst_l[] = {
813 "init", "cmn", "lane", "pcs_apb", "pma_apb"
814};
815
816static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
Jonas Karlman4c17f662024-05-04 19:43:02 +0000817 .num_phys = 2,
818 .phy_ids = {
819 0xfed80000,
820 0xfed90000,
821 },
Frank Wang93543942023-05-29 13:01:33 +0300822 .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
823 .rst_list = rk3588_udphy_rst_l,
824 .grfcfg = {
825 /* u2phy-grf */
826 .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 },
827 .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 },
828
829 /* usb-grf */
830 .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 },
831 .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 },
832
833 /* usbdpphy-grf */
834 .low_pwrn = { 0x0004, 13, 13, 0, 1 },
835 .rx_lfps = { 0x0004, 14, 14, 0, 1 },
836 },
837 .combophy_init = rk3588_udphy_init,
838};
839
840static const struct udevice_id rockchip_udphy_dt_match[] = {
841 {
842 .compatible = "rockchip,rk3588-usbdp-phy",
843 .data = (ulong)&rk3588_udphy_cfgs
844 },
845 { /* sentinel */ }
846};
847
Frank Wang93543942023-05-29 13:01:33 +0300848U_BOOT_DRIVER(rockchip_udphy) = {
849 .name = "rockchip_udphy",
850 .id = UCLASS_PHY,
851 .of_match = rockchip_udphy_dt_match,
852 .probe = rockchip_udphy_probe,
Jonas Karlmanc94fca32024-05-04 19:43:04 +0000853 .ops = &rockchip_u3phy_ops,
Frank Wang93543942023-05-29 13:01:33 +0300854 .priv_auto = sizeof(struct rockchip_udphy),
855};