Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Davinci MMC Controller Driver |
| 4 | * |
| 5 | * Copyright (C) 2010 Texas Instruments Incorporated |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <config.h> |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 9 | #include <dm.h> |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 10 | #include <errno.h> |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 11 | #include <mmc.h> |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 12 | #include <command.h> |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 13 | #include <part.h> |
| 14 | #include <malloc.h> |
| 15 | #include <asm/io.h> |
| 16 | #include <asm/arch/sdmmc_defs.h> |
Adam Ford | 7d9bdcc | 2018-09-03 03:47:52 -0500 | [diff] [blame] | 17 | #include <asm-generic/gpio.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 18 | #include <linux/delay.h> |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 19 | |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 20 | #define WATCHDOG_COUNT (100000) |
| 21 | |
| 22 | #define get_val(addr) REG(addr) |
| 23 | #define set_val(addr, val) REG(addr) = (val) |
| 24 | #define set_bit(addr, val) set_val((addr), (get_val(addr) | (val))) |
| 25 | #define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val))) |
| 26 | |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 27 | #ifdef CONFIG_DM_MMC |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 28 | /* Davinci MMC board definitions */ |
| 29 | struct davinci_mmc_priv { |
| 30 | struct davinci_mmc_regs *reg_base; /* Register base address */ |
| 31 | uint input_clk; /* Input clock to MMC controller */ |
Adam Ford | 7d9bdcc | 2018-09-03 03:47:52 -0500 | [diff] [blame] | 32 | struct gpio_desc cd_gpio; /* Card Detect GPIO */ |
| 33 | struct gpio_desc wp_gpio; /* Write Protect GPIO */ |
Tom Rini | 131f4ad | 2020-01-03 12:00:04 -0500 | [diff] [blame] | 34 | }; |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 35 | #endif |
| 36 | |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 37 | /* Set davinci clock prescalar value based on the required clock in HZ */ |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 38 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 39 | static void dmmc_set_clock(struct mmc *mmc, uint clock) |
| 40 | { |
| 41 | struct davinci_mmc *host = mmc->priv; |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 42 | #else |
| 43 | |
| 44 | static void davinci_mmc_set_clock(struct udevice *dev, uint clock) |
| 45 | { |
| 46 | struct davinci_mmc_priv *host = dev_get_priv(dev); |
| 47 | struct mmc *mmc = mmc_get_mmc_dev(dev); |
| 48 | #endif |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 49 | struct davinci_mmc_regs *regs = host->reg_base; |
| 50 | uint clkrt, sysclk2, act_clock; |
| 51 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 52 | if (clock < mmc->cfg->f_min) |
| 53 | clock = mmc->cfg->f_min; |
| 54 | if (clock > mmc->cfg->f_max) |
| 55 | clock = mmc->cfg->f_max; |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 56 | |
| 57 | set_val(®s->mmcclk, 0); |
| 58 | sysclk2 = host->input_clk; |
| 59 | clkrt = (sysclk2 / (2 * clock)) - 1; |
| 60 | |
| 61 | /* Calculate the actual clock for the divider used */ |
| 62 | act_clock = (sysclk2 / (2 * (clkrt + 1))); |
| 63 | |
| 64 | /* Adjust divider if actual clock exceeds the required clock */ |
| 65 | if (act_clock > clock) |
| 66 | clkrt++; |
| 67 | |
| 68 | /* check clock divider boundary and correct it */ |
| 69 | if (clkrt > 0xFF) |
| 70 | clkrt = 0xFF; |
| 71 | |
| 72 | set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN)); |
| 73 | } |
| 74 | |
| 75 | /* Status bit wait loop for MMCST1 */ |
| 76 | static int |
| 77 | dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status) |
| 78 | { |
Heiko Schocher | 1a3d749 | 2011-10-30 19:15:53 +0000 | [diff] [blame] | 79 | uint wdog = WATCHDOG_COUNT; |
| 80 | |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 81 | while (--wdog && ((get_val(®s->mmcst1) & status) != status)) |
| 82 | udelay(10); |
| 83 | |
| 84 | if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT)) |
| 85 | udelay(100); |
| 86 | |
| 87 | if (wdog == 0) |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 88 | return -ECOMM; |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 89 | |
| 90 | return 0; |
| 91 | } |
| 92 | |
| 93 | /* Busy bit wait loop for MMCST1 */ |
| 94 | static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs) |
| 95 | { |
Heiko Schocher | 1a3d749 | 2011-10-30 19:15:53 +0000 | [diff] [blame] | 96 | uint wdog = WATCHDOG_COUNT; |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 97 | |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 98 | while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY)) |
| 99 | udelay(10); |
| 100 | |
| 101 | if (wdog == 0) |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 102 | return -ECOMM; |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 103 | |
| 104 | return 0; |
| 105 | } |
| 106 | |
| 107 | /* Status bit wait loop for MMCST0 - Checks for error bits as well */ |
| 108 | static int dmmc_check_status(volatile struct davinci_mmc_regs *regs, |
| 109 | uint *cur_st, uint st_ready, uint st_error) |
| 110 | { |
| 111 | uint wdog = WATCHDOG_COUNT; |
| 112 | uint mmcstatus = *cur_st; |
| 113 | |
| 114 | while (wdog--) { |
| 115 | if (mmcstatus & st_ready) { |
| 116 | *cur_st = mmcstatus; |
| 117 | mmcstatus = get_val(®s->mmcst1); |
| 118 | return 0; |
| 119 | } else if (mmcstatus & st_error) { |
| 120 | if (mmcstatus & MMCST0_TOUTRS) |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 121 | return -ETIMEDOUT; |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 122 | printf("[ ST0 ERROR %x]\n", mmcstatus); |
| 123 | /* |
| 124 | * Ignore CRC errors as some MMC cards fail to |
| 125 | * initialize on DM365-EVM on the SD1 slot |
| 126 | */ |
| 127 | if (mmcstatus & MMCST0_CRCRS) |
| 128 | return 0; |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 129 | return -ECOMM; |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 130 | } |
| 131 | udelay(10); |
| 132 | |
| 133 | mmcstatus = get_val(®s->mmcst0); |
| 134 | } |
| 135 | |
| 136 | printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus, |
| 137 | get_val(®s->mmcst1)); |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 138 | return -ECOMM; |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | /* |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 142 | * Sends a command out on the bus. Takes the device pointer, |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 143 | * a command pointer, and an optional data pointer. |
| 144 | */ |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 145 | #if !CONFIG_IS_ENABLED(DM_MMC) |
| 146 | static int dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 147 | { |
| 148 | struct davinci_mmc *host = mmc->priv; |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 149 | #else |
| 150 | static int |
| 151 | davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) |
| 152 | { |
| 153 | struct davinci_mmc_priv *host = dev_get_priv(dev); |
| 154 | #endif |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 155 | volatile struct davinci_mmc_regs *regs = host->reg_base; |
| 156 | uint mmcstatus, status_rdy, status_err; |
| 157 | uint i, cmddata, bytes_left = 0; |
| 158 | int fifo_words, fifo_bytes, err; |
| 159 | char *data_buf = NULL; |
| 160 | |
| 161 | /* Clear status registers */ |
| 162 | mmcstatus = get_val(®s->mmcst0); |
Bartosz Golaszewski | 3dffb44 | 2019-11-14 16:10:28 +0100 | [diff] [blame] | 163 | fifo_words = 16; |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 164 | fifo_bytes = fifo_words << 2; |
| 165 | |
| 166 | /* Wait for any previous busy signal to be cleared */ |
| 167 | dmmc_busy_wait(regs); |
| 168 | |
| 169 | cmddata = cmd->cmdidx; |
| 170 | cmddata |= MMCCMD_PPLEN; |
| 171 | |
| 172 | /* Send init clock for CMD0 */ |
| 173 | if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE) |
| 174 | cmddata |= MMCCMD_INITCK; |
| 175 | |
| 176 | switch (cmd->resp_type) { |
| 177 | case MMC_RSP_R1b: |
| 178 | cmddata |= MMCCMD_BSYEXP; |
| 179 | /* Fall-through */ |
| 180 | case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */ |
| 181 | cmddata |= MMCCMD_RSPFMT_R1567; |
| 182 | break; |
| 183 | case MMC_RSP_R2: |
| 184 | cmddata |= MMCCMD_RSPFMT_R2; |
| 185 | break; |
| 186 | case MMC_RSP_R3: /* R3, R4 */ |
| 187 | cmddata |= MMCCMD_RSPFMT_R3; |
| 188 | break; |
| 189 | } |
| 190 | |
| 191 | set_val(®s->mmcim, 0); |
| 192 | |
| 193 | if (data) { |
| 194 | /* clear previous data transfer if any and set new one */ |
| 195 | bytes_left = (data->blocksize * data->blocks); |
| 196 | |
| 197 | /* Reset FIFO - Always use 32 byte fifo threshold */ |
| 198 | set_val(®s->mmcfifoctl, |
| 199 | (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST)); |
| 200 | |
Bartosz Golaszewski | 3dffb44 | 2019-11-14 16:10:28 +0100 | [diff] [blame] | 201 | cmddata |= MMCCMD_DMATRIG; |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 202 | |
| 203 | cmddata |= MMCCMD_WDATX; |
| 204 | if (data->flags == MMC_DATA_READ) { |
| 205 | set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV); |
| 206 | } else if (data->flags == MMC_DATA_WRITE) { |
| 207 | set_val(®s->mmcfifoctl, |
| 208 | (MMCFIFOCTL_FIFOLEV | |
| 209 | MMCFIFOCTL_FIFODIR)); |
| 210 | cmddata |= MMCCMD_DTRW; |
| 211 | } |
| 212 | |
| 213 | set_val(®s->mmctod, 0xFFFF); |
| 214 | set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK)); |
| 215 | set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK)); |
| 216 | |
| 217 | if (data->flags == MMC_DATA_WRITE) { |
| 218 | uint val; |
| 219 | data_buf = (char *)data->src; |
| 220 | /* For write, fill FIFO with data before issue of CMD */ |
| 221 | for (i = 0; (i < fifo_words) && bytes_left; i++) { |
| 222 | memcpy((char *)&val, data_buf, 4); |
| 223 | set_val(®s->mmcdxr, val); |
| 224 | data_buf += 4; |
| 225 | bytes_left -= 4; |
| 226 | } |
| 227 | } |
| 228 | } else { |
| 229 | set_val(®s->mmcblen, 0); |
| 230 | set_val(®s->mmcnblk, 0); |
| 231 | } |
| 232 | |
| 233 | set_val(®s->mmctor, 0x1FFF); |
| 234 | |
| 235 | /* Send the command */ |
| 236 | set_val(®s->mmcarghl, cmd->cmdarg); |
| 237 | set_val(®s->mmccmd, cmddata); |
| 238 | |
| 239 | status_rdy = MMCST0_RSPDNE; |
| 240 | status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD | |
| 241 | MMCST0_CRCWR | MMCST0_CRCRD); |
| 242 | if (cmd->resp_type & MMC_RSP_CRC) |
| 243 | status_err |= MMCST0_CRCRS; |
| 244 | |
| 245 | mmcstatus = get_val(®s->mmcst0); |
| 246 | err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err); |
| 247 | if (err) |
| 248 | return err; |
| 249 | |
| 250 | /* For R1b wait for busy done */ |
| 251 | if (cmd->resp_type == MMC_RSP_R1b) |
| 252 | dmmc_busy_wait(regs); |
| 253 | |
| 254 | /* Collect response from controller for specific commands */ |
| 255 | if (mmcstatus & MMCST0_RSPDNE) { |
| 256 | /* Copy the response to the response buffer */ |
| 257 | if (cmd->resp_type & MMC_RSP_136) { |
| 258 | cmd->response[0] = get_val(®s->mmcrsp67); |
| 259 | cmd->response[1] = get_val(®s->mmcrsp45); |
| 260 | cmd->response[2] = get_val(®s->mmcrsp23); |
| 261 | cmd->response[3] = get_val(®s->mmcrsp01); |
| 262 | } else if (cmd->resp_type & MMC_RSP_PRESENT) { |
| 263 | cmd->response[0] = get_val(®s->mmcrsp67); |
| 264 | } |
| 265 | } |
| 266 | |
| 267 | if (data == NULL) |
| 268 | return 0; |
| 269 | |
| 270 | if (data->flags == MMC_DATA_READ) { |
| 271 | /* check for DATDNE along with DRRDY as the controller might |
| 272 | * set the DATDNE without DRRDY for smaller transfers with |
| 273 | * less than FIFO threshold bytes |
| 274 | */ |
| 275 | status_rdy = MMCST0_DRRDY | MMCST0_DATDNE; |
| 276 | status_err = MMCST0_TOUTRD | MMCST0_CRCRD; |
| 277 | data_buf = data->dest; |
| 278 | } else { |
| 279 | status_rdy = MMCST0_DXRDY | MMCST0_DATDNE; |
| 280 | status_err = MMCST0_CRCWR; |
| 281 | } |
| 282 | |
| 283 | /* Wait until all of the blocks are transferred */ |
| 284 | while (bytes_left) { |
| 285 | err = dmmc_check_status(regs, &mmcstatus, status_rdy, |
| 286 | status_err); |
| 287 | if (err) |
| 288 | return err; |
| 289 | |
| 290 | if (data->flags == MMC_DATA_READ) { |
| 291 | /* |
| 292 | * MMC controller sets the Data receive ready bit |
| 293 | * (DRRDY) in MMCST0 even before the entire FIFO is |
| 294 | * full. This results in erratic behavior if we start |
| 295 | * reading the FIFO soon after DRRDY. Wait for the |
| 296 | * FIFO full bit in MMCST1 for proper FIFO clearing. |
| 297 | */ |
| 298 | if (bytes_left > fifo_bytes) |
| 299 | dmmc_wait_fifo_status(regs, 0x4a); |
Davide Bonfanti | f7289ee | 2012-11-29 01:06:53 +0000 | [diff] [blame] | 300 | else if (bytes_left == fifo_bytes) { |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 301 | dmmc_wait_fifo_status(regs, 0x40); |
Davide Bonfanti | f7289ee | 2012-11-29 01:06:53 +0000 | [diff] [blame] | 302 | if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD) |
| 303 | udelay(600); |
| 304 | } |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 305 | |
| 306 | for (i = 0; bytes_left && (i < fifo_words); i++) { |
| 307 | cmddata = get_val(®s->mmcdrr); |
| 308 | memcpy(data_buf, (char *)&cmddata, 4); |
| 309 | data_buf += 4; |
| 310 | bytes_left -= 4; |
| 311 | } |
| 312 | } else { |
| 313 | /* |
| 314 | * MMC controller sets the Data transmit ready bit |
| 315 | * (DXRDY) in MMCST0 even before the entire FIFO is |
| 316 | * empty. This results in erratic behavior if we start |
| 317 | * writing the FIFO soon after DXRDY. Wait for the |
| 318 | * FIFO empty bit in MMCST1 for proper FIFO clearing. |
| 319 | */ |
| 320 | dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP); |
| 321 | for (i = 0; bytes_left && (i < fifo_words); i++) { |
| 322 | memcpy((char *)&cmddata, data_buf, 4); |
| 323 | set_val(®s->mmcdxr, cmddata); |
| 324 | data_buf += 4; |
| 325 | bytes_left -= 4; |
| 326 | } |
| 327 | dmmc_busy_wait(regs); |
| 328 | } |
| 329 | } |
| 330 | |
| 331 | err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err); |
| 332 | if (err) |
| 333 | return err; |
| 334 | |
| 335 | return 0; |
| 336 | } |
| 337 | |
| 338 | /* Initialize Davinci MMC controller */ |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 339 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 340 | static int dmmc_init(struct mmc *mmc) |
| 341 | { |
| 342 | struct davinci_mmc *host = mmc->priv; |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 343 | #else |
| 344 | static int davinci_dm_mmc_init(struct udevice *dev) |
| 345 | { |
| 346 | struct davinci_mmc_priv *host = dev_get_priv(dev); |
| 347 | #endif |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 348 | struct davinci_mmc_regs *regs = host->reg_base; |
| 349 | |
| 350 | /* Clear status registers explicitly - soft reset doesn't clear it |
| 351 | * If Uboot is invoked from UBL with SDMMC Support, the status |
| 352 | * registers can have uncleared bits |
| 353 | */ |
| 354 | get_val(®s->mmcst0); |
| 355 | get_val(®s->mmcst1); |
| 356 | |
| 357 | /* Hold software reset */ |
| 358 | set_bit(®s->mmcctl, MMCCTL_DATRST); |
| 359 | set_bit(®s->mmcctl, MMCCTL_CMDRST); |
| 360 | udelay(10); |
| 361 | |
| 362 | set_val(®s->mmcclk, 0x0); |
| 363 | set_val(®s->mmctor, 0x1FFF); |
| 364 | set_val(®s->mmctod, 0xFFFF); |
| 365 | |
| 366 | /* Clear software reset */ |
| 367 | clear_bit(®s->mmcctl, MMCCTL_DATRST); |
| 368 | clear_bit(®s->mmcctl, MMCCTL_CMDRST); |
| 369 | |
| 370 | udelay(10); |
| 371 | |
| 372 | /* Reset FIFO - Always use the maximum fifo threshold */ |
| 373 | set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST)); |
| 374 | set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV); |
| 375 | |
| 376 | return 0; |
| 377 | } |
| 378 | |
Masahiro Yamada | 0a78017 | 2017-05-09 20:31:39 +0900 | [diff] [blame] | 379 | /* Set buswidth or clock as indicated by the MMC framework */ |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 380 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Jaehoon Chung | b6cd1d3 | 2016-12-30 15:30:16 +0900 | [diff] [blame] | 381 | static int dmmc_set_ios(struct mmc *mmc) |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 382 | { |
| 383 | struct davinci_mmc *host = mmc->priv; |
| 384 | struct davinci_mmc_regs *regs = host->reg_base; |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 385 | #else |
| 386 | static int davinci_mmc_set_ios(struct udevice *dev) |
| 387 | { |
| 388 | struct mmc *mmc = mmc_get_mmc_dev(dev); |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 389 | |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 390 | struct davinci_mmc_priv *host = dev_get_priv(dev); |
| 391 | struct davinci_mmc_regs *regs = host->reg_base; |
| 392 | #endif |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 393 | /* Set the bus width */ |
| 394 | if (mmc->bus_width == 4) |
| 395 | set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT); |
| 396 | else |
| 397 | clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT); |
| 398 | |
| 399 | /* Set clock speed */ |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 400 | if (mmc->clock) { |
| 401 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 402 | dmmc_set_clock(mmc, mmc->clock); |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 403 | #else |
| 404 | davinci_mmc_set_clock(dev, mmc->clock); |
| 405 | #endif |
| 406 | } |
Jaehoon Chung | b6cd1d3 | 2016-12-30 15:30:16 +0900 | [diff] [blame] | 407 | return 0; |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 408 | } |
| 409 | |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 410 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 411 | static const struct mmc_ops dmmc_ops = { |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 412 | .send_cmd = dmmc_send_cmd, |
| 413 | .set_ios = dmmc_set_ios, |
| 414 | .init = dmmc_init, |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 415 | }; |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 416 | #else |
Adam Ford | 7d9bdcc | 2018-09-03 03:47:52 -0500 | [diff] [blame] | 417 | |
| 418 | static int davinci_mmc_getcd(struct udevice *dev) |
| 419 | { |
| 420 | int value = -1; |
| 421 | #if CONFIG_IS_ENABLED(DM_GPIO) |
| 422 | struct davinci_mmc_priv *priv = dev_get_priv(dev); |
| 423 | value = dm_gpio_get_value(&priv->cd_gpio); |
| 424 | #endif |
| 425 | /* if no CD return as 1 */ |
| 426 | if (value < 0) |
| 427 | return 1; |
| 428 | |
| 429 | return value; |
| 430 | } |
| 431 | |
| 432 | static int davinci_mmc_getwp(struct udevice *dev) |
| 433 | { |
| 434 | int value = -1; |
| 435 | #if CONFIG_IS_ENABLED(DM_GPIO) |
| 436 | struct davinci_mmc_priv *priv = dev_get_priv(dev); |
| 437 | |
| 438 | value = dm_gpio_get_value(&priv->wp_gpio); |
| 439 | #endif |
| 440 | /* if no WP return as 0 */ |
| 441 | if (value < 0) |
| 442 | return 0; |
| 443 | |
| 444 | return value; |
| 445 | } |
| 446 | |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 447 | static const struct dm_mmc_ops davinci_mmc_ops = { |
| 448 | .send_cmd = davinci_mmc_send_cmd, |
| 449 | .set_ios = davinci_mmc_set_ios, |
Adam Ford | 7d9bdcc | 2018-09-03 03:47:52 -0500 | [diff] [blame] | 450 | .get_cd = davinci_mmc_getcd, |
| 451 | .get_wp = davinci_mmc_getwp, |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 452 | }; |
| 453 | #endif |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 454 | |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 455 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 456 | /* Called from board_mmc_init during startup. Can be called multiple times |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 457 | * depending on the number of slots available on board and controller |
| 458 | */ |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 459 | int davinci_mmc_init(struct bd_info *bis, struct davinci_mmc *host) |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 460 | { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 461 | host->cfg.name = "davinci"; |
| 462 | host->cfg.ops = &dmmc_ops; |
| 463 | host->cfg.f_min = 200000; |
| 464 | host->cfg.f_max = 25000000; |
| 465 | host->cfg.voltages = host->voltages; |
| 466 | host->cfg.host_caps = host->host_caps; |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 467 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 468 | host->cfg.b_max = DAVINCI_MAX_BLOCKS; |
John Rigby | f2f4366 | 2011-04-18 05:50:08 +0000 | [diff] [blame] | 469 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 470 | mmc_create(&host->cfg, host); |
Sandeep Paulraj | 5034717 | 2010-12-20 20:01:21 -0500 | [diff] [blame] | 471 | |
| 472 | return 0; |
| 473 | } |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 474 | #else |
| 475 | |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 476 | static int davinci_mmc_probe(struct udevice *dev) |
| 477 | { |
| 478 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 479 | struct davinci_mmc_plat *plat = dev_get_plat(dev); |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 480 | struct davinci_mmc_priv *priv = dev_get_priv(dev); |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 481 | |
Faiz Abbas | ae01d76 | 2020-05-22 07:32:28 +0530 | [diff] [blame] | 482 | priv->reg_base = plat->reg_base; |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 483 | priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID); |
Adam Ford | 7d9bdcc | 2018-09-03 03:47:52 -0500 | [diff] [blame] | 484 | #if CONFIG_IS_ENABLED(DM_GPIO) |
| 485 | /* These GPIOs are optional */ |
| 486 | gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); |
| 487 | gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); |
| 488 | #endif |
Tom Rini | 131f4ad | 2020-01-03 12:00:04 -0500 | [diff] [blame] | 489 | upriv->mmc = &plat->mmc; |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 490 | |
| 491 | return davinci_dm_mmc_init(dev); |
| 492 | } |
| 493 | |
| 494 | static int davinci_mmc_bind(struct udevice *dev) |
| 495 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 496 | struct davinci_mmc_plat *plat = dev_get_plat(dev); |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 497 | |
Tom Rini | 131f4ad | 2020-01-03 12:00:04 -0500 | [diff] [blame] | 498 | return mmc_bind(dev, &plat->mmc, &plat->cfg); |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 499 | } |
| 500 | |
Faiz Abbas | ae01d76 | 2020-05-22 07:32:28 +0530 | [diff] [blame] | 501 | #if CONFIG_IS_ENABLED(OF_CONTROL) |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 502 | static int davinci_mmc_of_to_plat(struct udevice *dev) |
Faiz Abbas | ae01d76 | 2020-05-22 07:32:28 +0530 | [diff] [blame] | 503 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 504 | struct davinci_mmc_plat *plat = dev_get_plat(dev); |
Faiz Abbas | ae01d76 | 2020-05-22 07:32:28 +0530 | [diff] [blame] | 505 | struct mmc_config *cfg = &plat->cfg; |
| 506 | |
Johan Jonker | 8d5d8e0 | 2023-03-13 01:32:04 +0100 | [diff] [blame] | 507 | plat->reg_base = dev_read_addr_ptr(dev); |
Faiz Abbas | ae01d76 | 2020-05-22 07:32:28 +0530 | [diff] [blame] | 508 | cfg->f_min = 200000; |
| 509 | cfg->f_max = 25000000; |
| 510 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34, |
| 511 | cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */ |
| 512 | cfg->b_max = DAVINCI_MAX_BLOCKS; |
| 513 | cfg->name = "da830-mmc"; |
| 514 | |
| 515 | return 0; |
| 516 | } |
| 517 | |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 518 | static const struct udevice_id davinci_mmc_ids[] = { |
Bartosz Golaszewski | 3dffb44 | 2019-11-14 16:10:28 +0100 | [diff] [blame] | 519 | { .compatible = "ti,da830-mmc" }, |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 520 | {}, |
| 521 | }; |
Faiz Abbas | ae01d76 | 2020-05-22 07:32:28 +0530 | [diff] [blame] | 522 | #endif |
Walter Lozano | 2901ac6 | 2020-06-25 01:10:04 -0300 | [diff] [blame] | 523 | U_BOOT_DRIVER(ti_da830_mmc) = { |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 524 | .name = "davinci_mmc", |
| 525 | .id = UCLASS_MMC, |
Faiz Abbas | ae01d76 | 2020-05-22 07:32:28 +0530 | [diff] [blame] | 526 | #if CONFIG_IS_ENABLED(OF_CONTROL) |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 527 | .of_match = davinci_mmc_ids, |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 528 | .plat_auto = sizeof(struct davinci_mmc_plat), |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 529 | .of_to_plat = davinci_mmc_of_to_plat, |
Faiz Abbas | ae01d76 | 2020-05-22 07:32:28 +0530 | [diff] [blame] | 530 | #endif |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 531 | #if CONFIG_BLK |
| 532 | .bind = davinci_mmc_bind, |
| 533 | #endif |
| 534 | .probe = davinci_mmc_probe, |
| 535 | .ops = &davinci_mmc_ops, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 536 | .priv_auto = sizeof(struct davinci_mmc_priv), |
Faiz Abbas | ae01d76 | 2020-05-22 07:32:28 +0530 | [diff] [blame] | 537 | #if !CONFIG_IS_ENABLED(OF_CONTROL) |
| 538 | .flags = DM_FLAG_PRE_RELOC, |
| 539 | #endif |
Adam Ford | 8ce7bdd | 2018-08-09 06:15:12 -0500 | [diff] [blame] | 540 | }; |
| 541 | #endif |