| Michael Walle | 898a8be | 2021-03-26 19:40:59 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | |
| Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 3 | #include <config.h> |
| Michael Walle | 898a8be | 2021-03-26 19:40:59 +0100 | [diff] [blame] | 4 | #include <asm/global_data.h> |
| Michael Walle | bf9c73c | 2022-08-23 11:30:15 +0200 | [diff] [blame] | 5 | #include <asm/io.h> |
| 6 | |
| 7 | #include "sl28.h" |
| Michael Walle | 898a8be | 2021-03-26 19:40:59 +0100 | [diff] [blame] | 8 | |
| 9 | DECLARE_GLOBAL_DATA_PTR; |
| 10 | |
| 11 | u32 get_lpuart_clk(void) |
| 12 | { |
| 13 | return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV; |
| 14 | } |
| Michael Walle | bf9c73c | 2022-08-23 11:30:15 +0200 | [diff] [blame] | 15 | |
| 16 | enum boot_source sl28_boot_source(void) |
| 17 | { |
| 18 | u32 rcw_src = in_le32(DCFG_BASE + DCFG_PORSR1) & DCFG_PORSR1_RCW_SRC; |
| 19 | |
| 20 | switch (rcw_src) { |
| 21 | case DCFG_PORSR1_RCW_SRC_SDHC1: |
| 22 | return BOOT_SOURCE_SDHC; |
| 23 | case DCFG_PORSR1_RCW_SRC_SDHC2: |
| 24 | return BOOT_SOURCE_MMC; |
| 25 | case DCFG_PORSR1_RCW_SRC_I2C: |
| 26 | return BOOT_SOURCE_I2C; |
| 27 | case DCFG_PORSR1_RCW_SRC_FSPI_NOR: |
| 28 | return BOOT_SOURCE_SPI; |
| 29 | default: |
| 30 | debug("unknown bootsource (%08x)\n", rcw_src); |
| 31 | return BOOT_SOURCE_UNKNOWN; |
| 32 | } |
| 33 | } |