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git01.mediatek.com / filogic / uboot / cd506ef7cd1c1083fca7c8f9fa80df05b8af7db8 / . / dts / upstream / src / arm / microchip / lan966x.dtsi
blob: 05b73f7cf0c7734d326fea29d96d62b44b56aa5f [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
4 *
5 * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
6 *
7 * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
8 *
9 */
10
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/mfd/atmel-flexcom.h>
14#include <dt-bindings/dma/at91.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/clock/microchip,lan966x.h>
17
18/ {
19 model = "Microchip LAN966 family SoC";
20 compatible = "microchip,lan966";
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a7";
32 clock-frequency = <600000000>;
33 reg = <0x0>;
34 };
35 };
36
37 clocks {
38 sys_clk: sys_clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <165625000>;
42 };
43
44 cpu_clk: cpu_clk {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <600000000>;
48 };
49
50 ddr_clk: ddr_clk {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <300000000>;
54 };
55
56 nic_clk: nic_clk {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <200000000>;
60 };
61 };
62
63 clks: clock-controller@e00c00a8 {
64 compatible = "microchip,lan966x-gck";
65 #clock-cells = <1>;
66 clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
67 clock-names = "cpu", "ddr", "sys";
68 reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>;
69 };
70
71 timer {
72 compatible = "arm,armv7-timer";
73 interrupt-parent = <&gic>;
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
78 clock-frequency = <37500000>;
79 };
80
81 soc {
82 compatible = "simple-bus";
83 #address-cells = <1>;
84 #size-cells = <1>;
85 ranges;
86
87 udc: usb@200000 {
88 compatible = "microchip,lan9662-udc",
89 "atmel,sama5d3-udc";
90 reg = <0x00200000 0x80000>,
91 <0xe0808000 0x400>;
92 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
93 clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>;
94 clock-names = "pclk", "hclk";
95 status = "disabled";
96 };
97
98 switch: switch@e0000000 {
99 compatible = "microchip,lan966x-switch";
100 reg = <0xe0000000 0x0100000>,
101 <0xe2000000 0x0800000>;
102 reg-names = "cpu", "gcb";
103 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-names = "xtr", "fdma", "ana", "ptp",
109 "ptp-ext";
110 resets = <&reset 0>;
111 reset-names = "switch";
112 status = "disabled";
113
114 ethernet-ports {
115 #address-cells = <1>;
116 #size-cells = <0>;
117
118 port0: port@0 {
119 reg = <0>;
120 status = "disabled";
121 };
122
123 port1: port@1 {
124 reg = <1>;
125 status = "disabled";
126 };
127
128 port2: port@2 {
129 reg = <2>;
130 status = "disabled";
131 };
132
133 port3: port@3 {
134 reg = <3>;
135 status = "disabled";
136 };
137
138 port4: port@4 {
139 reg = <4>;
140 status = "disabled";
141 };
142
143 port5: port@5 {
144 reg = <5>;
145 status = "disabled";
146 };
147
148 port6: port@6 {
149 reg = <6>;
150 status = "disabled";
151 };
152
153 port7: port@7 {
154 reg = <7>;
155 status = "disabled";
156 };
157 };
158 };
159
160 otp: otp@e0021000 {
161 compatible = "microchip,lan9668-otpc", "microchip,lan9662-otpc";
162 reg = <0xe0021000 0x300>;
163 };
164
165 flx0: flexcom@e0040000 {
166 compatible = "atmel,sama5d2-flexcom";
167 reg = <0xe0040000 0x100>;
168 clocks = <&clks GCK_ID_FLEXCOM0>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0xe0040000 0x800>;
172 status = "disabled";
173
174 usart0: serial@200 {
175 compatible = "atmel,at91sam9260-usart";
176 reg = <0x200 0x200>;
177 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
178 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
179 <&dma0 AT91_XDMAC_DT_PERID(2)>;
180 dma-names = "tx", "rx";
181 clocks = <&nic_clk>;
182 clock-names = "usart";
183 atmel,fifo-size = <32>;
184 status = "disabled";
185 };
186
187 spi0: spi@400 {
188 compatible = "atmel,at91rm9200-spi";
189 reg = <0x400 0x200>;
190 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
191 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
192 <&dma0 AT91_XDMAC_DT_PERID(2)>;
193 dma-names = "tx", "rx";
194 clocks = <&nic_clk>;
195 clock-names = "spi_clk";
196 atmel,fifo-size = <32>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 status = "disabled";
200 };
201
202 i2c0: i2c@600 {
203 compatible = "microchip,sam9x60-i2c";
204 reg = <0x600 0x200>;
205 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
206 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
207 <&dma0 AT91_XDMAC_DT_PERID(2)>;
208 dma-names = "tx", "rx";
209 clocks = <&nic_clk>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212 status = "disabled";
213 };
214 };
215
216 flx1: flexcom@e0044000 {
217 compatible = "atmel,sama5d2-flexcom";
218 reg = <0xe0044000 0x100>;
219 clocks = <&clks GCK_ID_FLEXCOM1>;
220 #address-cells = <1>;
221 #size-cells = <1>;
222 ranges = <0x0 0xe0044000 0x800>;
223 status = "disabled";
224
225 usart1: serial@200 {
226 compatible = "atmel,at91sam9260-usart";
227 reg = <0x200 0x200>;
228 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
229 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
230 <&dma0 AT91_XDMAC_DT_PERID(4)>;
231 dma-names = "tx", "rx";
232 clocks = <&nic_clk>;
233 clock-names = "usart";
234 atmel,fifo-size = <32>;
235 status = "disabled";
236 };
237
238 spi1: spi@400 {
239 compatible = "atmel,at91rm9200-spi";
240 reg = <0x400 0x200>;
241 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
242 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
243 <&dma0 AT91_XDMAC_DT_PERID(4)>;
244 dma-names = "tx", "rx";
245 clocks = <&nic_clk>;
246 clock-names = "spi_clk";
247 atmel,fifo-size = <32>;
248 #address-cells = <1>;
249 #size-cells = <0>;
250 status = "disabled";
251 };
252
253 i2c1: i2c@600 {
254 compatible = "microchip,sam9x60-i2c";
255 reg = <0x600 0x200>;
256 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
257 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
258 <&dma0 AT91_XDMAC_DT_PERID(4)>;
259 dma-names = "tx", "rx";
260 clocks = <&nic_clk>;
261 #address-cells = <1>;
262 #size-cells = <0>;
263 status = "disabled";
264 };
265 };
266
267 trng: rng@e0048000 {
268 compatible = "atmel,at91sam9g45-trng";
269 reg = <0xe0048000 0x100>;
270 clocks = <&nic_clk>;
271 };
272
273 aes: crypto@e004c000 {
274 compatible = "atmel,at91sam9g46-aes";
275 reg = <0xe004c000 0x100>;
276 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
277 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
278 <&dma0 AT91_XDMAC_DT_PERID(13)>;
279 dma-names = "tx", "rx";
280 clocks = <&nic_clk>;
281 clock-names = "aes_clk";
282 };
283
284 flx2: flexcom@e0060000 {
285 compatible = "atmel,sama5d2-flexcom";
286 reg = <0xe0060000 0x100>;
287 clocks = <&clks GCK_ID_FLEXCOM2>;
288 #address-cells = <1>;
289 #size-cells = <1>;
290 ranges = <0x0 0xe0060000 0x800>;
291 status = "disabled";
292
293 usart2: serial@200 {
294 compatible = "atmel,at91sam9260-usart";
295 reg = <0x200 0x200>;
296 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
297 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
298 <&dma0 AT91_XDMAC_DT_PERID(6)>;
299 dma-names = "tx", "rx";
300 clocks = <&nic_clk>;
301 clock-names = "usart";
302 atmel,fifo-size = <32>;
303 status = "disabled";
304 };
305
306 spi2: spi@400 {
307 compatible = "atmel,at91rm9200-spi";
308 reg = <0x400 0x200>;
309 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
310 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
311 <&dma0 AT91_XDMAC_DT_PERID(6)>;
312 dma-names = "tx", "rx";
313 clocks = <&nic_clk>;
314 clock-names = "spi_clk";
315 atmel,fifo-size = <32>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318 status = "disabled";
319 };
320
321 i2c2: i2c@600 {
322 compatible = "microchip,sam9x60-i2c";
323 reg = <0x600 0x200>;
324 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
325 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
326 <&dma0 AT91_XDMAC_DT_PERID(6)>;
327 dma-names = "tx", "rx";
328 clocks = <&nic_clk>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 status = "disabled";
332 };
333 };
334
335 flx3: flexcom@e0064000 {
336 compatible = "atmel,sama5d2-flexcom";
337 reg = <0xe0064000 0x100>;
338 clocks = <&clks GCK_ID_FLEXCOM3>;
339 #address-cells = <1>;
340 #size-cells = <1>;
341 ranges = <0x0 0xe0064000 0x800>;
342 status = "disabled";
343
344 usart3: serial@200 {
345 compatible = "atmel,at91sam9260-usart";
346 reg = <0x200 0x200>;
347 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
348 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
349 <&dma0 AT91_XDMAC_DT_PERID(8)>;
350 dma-names = "tx", "rx";
351 clocks = <&nic_clk>;
352 clock-names = "usart";
353 atmel,fifo-size = <32>;
354 status = "disabled";
355 };
356
357 spi3: spi@400 {
358 compatible = "atmel,at91rm9200-spi";
359 reg = <0x400 0x200>;
360 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
361 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
362 <&dma0 AT91_XDMAC_DT_PERID(8)>;
363 dma-names = "tx", "rx";
364 clocks = <&nic_clk>;
365 clock-names = "spi_clk";
366 atmel,fifo-size = <32>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 status = "disabled";
370 };
371
372 i2c3: i2c@600 {
373 compatible = "microchip,sam9x60-i2c";
374 reg = <0x600 0x200>;
375 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
376 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
377 <&dma0 AT91_XDMAC_DT_PERID(8)>;
378 dma-names = "tx", "rx";
379 clocks = <&nic_clk>;
380 #address-cells = <1>;
381 #size-cells = <0>;
382 status = "disabled";
383 };
384 };
385
386 dma0: dma-controller@e0068000 {
387 compatible = "microchip,sama7g5-dma";
388 reg = <0xe0068000 0x1000>;
389 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
390 #dma-cells = <1>;
391 clocks = <&nic_clk>;
392 clock-names = "dma_clk";
393 };
394
395 sha: crypto@e006c000 {
396 compatible = "atmel,at91sam9g46-sha";
397 reg = <0xe006c000 0xec>;
398 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
399 dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
400 dma-names = "tx";
401 clocks = <&nic_clk>;
402 clock-names = "sha_clk";
403 };
404
405 flx4: flexcom@e0070000 {
406 compatible = "atmel,sama5d2-flexcom";
407 reg = <0xe0070000 0x100>;
408 clocks = <&clks GCK_ID_FLEXCOM4>;
409 #address-cells = <1>;
410 #size-cells = <1>;
411 ranges = <0x0 0xe0070000 0x800>;
412 status = "disabled";
413
414 usart4: serial@200 {
415 compatible = "atmel,at91sam9260-usart";
416 reg = <0x200 0x200>;
417 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
418 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
419 <&dma0 AT91_XDMAC_DT_PERID(10)>;
420 dma-names = "tx", "rx";
421 clocks = <&nic_clk>;
422 clock-names = "usart";
423 atmel,fifo-size = <32>;
424 status = "disabled";
425 };
426
427 spi4: spi@400 {
428 compatible = "atmel,at91rm9200-spi";
429 reg = <0x400 0x200>;
430 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
431 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
432 <&dma0 AT91_XDMAC_DT_PERID(10)>;
433 dma-names = "tx", "rx";
434 clocks = <&nic_clk>;
435 clock-names = "spi_clk";
436 atmel,fifo-size = <32>;
437 #address-cells = <1>;
438 #size-cells = <0>;
439 status = "disabled";
440 };
441
442 i2c4: i2c@600 {
443 compatible = "microchip,sam9x60-i2c";
444 reg = <0x600 0x200>;
445 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
446 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
447 <&dma0 AT91_XDMAC_DT_PERID(10)>;
448 dma-names = "tx", "rx";
449 clocks = <&nic_clk>;
450 #address-cells = <1>;
451 #size-cells = <0>;
452 status = "disabled";
453 };
454 };
455
456 timer0: timer@e008c000 {
457 compatible = "snps,dw-apb-timer";
458 reg = <0xe008c000 0x400>;
459 clocks = <&nic_clk>;
460 clock-names = "timer";
461 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
462 };
463
464 watchdog: watchdog@e0090000 {
465 compatible = "snps,dw-wdt";
466 reg = <0xe0090000 0x1000>;
467 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&nic_clk>;
469 status = "disabled";
470 };
471
472 cpu_ctrl: syscon@e00c0000 {
473 compatible = "microchip,lan966x-cpu-syscon", "syscon";
474 reg = <0xe00c0000 0x350>;
475 };
476
477 can0: can@e081c000 {
478 compatible = "bosch,m_can";
479 reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
480 reg-names = "m_can", "message_ram";
481 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
483 interrupt-names = "int0", "int1";
484 clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
485 clock-names = "hclk", "cclk";
486 assigned-clocks = <&clks GCK_ID_MCAN0>;
487 assigned-clock-rates = <40000000>;
488 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
489 status = "disabled";
490 };
491
492 can1: can@e0820000 {
493 compatible = "bosch,m_can";
494 reg = <0xe0820000 0xfc>, <0x00100000 0x8000>;
495 reg-names = "m_can", "message_ram";
496 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
498 interrupt-names = "int0", "int1";
499 clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>;
500 clock-names = "hclk", "cclk";
501 assigned-clocks = <&clks GCK_ID_MCAN1>;
502 assigned-clock-rates = <40000000>;
503 bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>;
504 status = "disabled";
505 };
506
507 reset: reset-controller@e200400c {
508 compatible = "microchip,lan966x-switch-reset";
509 reg = <0xe200400c 0x4>;
510 reg-names = "gcb";
511 #reset-cells = <1>;
512 cpu-syscon = <&cpu_ctrl>;
513 };
514
515 gpio: pinctrl@e2004064 {
516 compatible = "microchip,lan966x-pinctrl";
517 reg = <0xe2004064 0xb4>,
518 <0xe2010024 0x138>;
519 resets = <&reset 0>;
520 reset-names = "switch";
521 gpio-controller;
522 #gpio-cells = <2>;
523 gpio-ranges = <&gpio 0 0 78>;
524 interrupt-controller;
525 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
526 #interrupt-cells = <2>;
527 };
528
529 mdio0: mdio@e2004118 {
530 compatible = "microchip,lan966x-miim";
531 #address-cells = <1>;
532 #size-cells = <0>;
533 reg = <0xe2004118 0x24>;
534 clocks = <&sys_clk>;
535 status = "disabled";
536 };
537
538 mdio1: mdio@e200413c {
539 compatible = "microchip,lan966x-miim";
540 #address-cells = <1>;
541 #size-cells = <0>;
542 reg = <0xe200413c 0x24>,
543 <0xe2010020 0x4>;
544 clocks = <&sys_clk>;
545 status = "disabled";
546
547 phy0: ethernet-phy@1 {
548 reg = <1>;
549 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
550 status = "disabled";
551 };
552
553 phy1: ethernet-phy@2 {
554 reg = <2>;
555 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
556 status = "disabled";
557 };
558 };
559
560 sgpio: gpio@e2004190 {
561 compatible = "microchip,sparx5-sgpio";
562 reg = <0xe2004190 0x118>;
563 clocks = <&sys_clk>;
564 resets = <&reset 0>;
565 reset-names = "switch";
566 #address-cells = <1>;
567 #size-cells = <0>;
568 status = "disabled";
569
570 sgpio_in: gpio@0 {
571 compatible = "microchip,sparx5-sgpio-bank";
572 reg = <0>;
573 gpio-controller;
574 #gpio-cells = <3>;
575 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
576 interrupt-controller;
577 #interrupt-cells = <3>;
578 };
579
580 sgpio_out: gpio@1 {
581 compatible = "microchip,sparx5-sgpio-bank";
582 reg = <1>;
583 gpio-controller;
584 #gpio-cells = <3>;
585 };
586 };
587
588 hwmon: hwmon@e2010180 {
589 compatible = "microchip,lan9668-hwmon";
590 reg = <0xe2010180 0xc>,
591 <0xe20042a8 0xc>;
592 reg-names = "pvt", "fan";
593 clocks = <&sys_clk>;
594 };
595
596 serdes: serdes@e202c000 {
597 compatible = "microchip,lan966x-serdes";
598 reg = <0xe202c000 0x9c>,
599 <0xe2004010 0x4>;
600 #phy-cells = <2>;
601 status = "disabled";
602 };
603
604 gic: interrupt-controller@e8c11000 {
605 compatible = "arm,gic-400", "arm,cortex-a7-gic";
606 #interrupt-cells = <3>;
607 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
608 interrupt-controller;
609 reg = <0xe8c11000 0x1000>,
610 <0xe8c12000 0x2000>,
611 <0xe8c14000 0x2000>,
612 <0xe8c16000 0x2000>;
613 };
614 };
615};