| Michal Simek | 4b066a1 | 2018-08-22 14:55:27 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0+ |
| 2 | |
| 3 | if ARCH_VERSAL |
| 4 | |
| 5 | config SYS_BOARD |
| 6 | string "Board name" |
| 7 | default "versal" |
| 8 | |
| 9 | config SYS_VENDOR |
| 10 | string "Vendor name" |
| 11 | default "xilinx" |
| 12 | |
| 13 | config SYS_SOC |
| 14 | default "versal" |
| 15 | |
| Michal Simek | 4b066a1 | 2018-08-22 14:55:27 +0200 | [diff] [blame] | 16 | config SYS_MALLOC_LEN |
| 17 | default 0x2000000 |
| 18 | |
| Michal Simek | 4b066a1 | 2018-08-22 14:55:27 +0200 | [diff] [blame] | 19 | config ZYNQ_SDHCI_MAX_FREQ |
| 20 | default 200000000 |
| 21 | |
| Michal Simek | f56f7d1 | 2019-01-28 11:12:41 +0100 | [diff] [blame] | 22 | config IOU_SWITCH_DIVISOR0 |
| 23 | hex "IOU switch divisor0" |
| 24 | default 0x20 |
| 25 | help |
| 26 | Setup time clock divisor for input clock. |
| 27 | |
| Siva Durga Prasad Paladugu | 775aa95 | 2019-01-08 21:47:26 +0530 | [diff] [blame] | 28 | config SYS_MEM_RSVD_FOR_MMU |
| 29 | bool "Reserve memory for MMU Table" |
| 30 | help |
| 31 | If defined this option is used to setup different space for |
| 32 | MMU table than the one which will be allocated during |
| 33 | relocation. |
| 34 | |
| Michal Simek | fe2eb11 | 2019-09-11 09:39:59 +0200 | [diff] [blame] | 35 | config DEFINE_TCM_OCM_MMAP |
| 36 | bool "Define TCM and OCM memory in MMU Table" |
| 37 | default y if MP |
| 38 | help |
| 39 | This option if enabled defines the TCM and OCM memory and its |
| 40 | memory attributes in MMU table entry. |
| 41 | |
| Michal Simek | dfcd21d | 2020-03-18 13:45:21 +0100 | [diff] [blame] | 42 | config VERSAL_NO_DDR |
| 43 | bool "Disable DDR MMU mapping" |
| 44 | help |
| 45 | This option configures MMU with no DDR to avoid speculative |
| 46 | access to DDR memory where DDR is not present. |
| 47 | |
| Michal Simek | 5f88485 | 2020-08-27 15:34:11 +0200 | [diff] [blame] | 48 | source "board/xilinx/Kconfig" |
| 49 | source "board/xilinx/versal/Kconfig" |
| 50 | |
| Michal Simek | 4b066a1 | 2018-08-22 14:55:27 +0200 | [diff] [blame] | 51 | endif |